PRCM Registers
6.2.3.12 OSCCFG Register (Offset = 38h) [reset = 0h]
OSCCFG is shown in
and described in
Oscillator Configuration
This register sets the period for Amplitude compensation requests sent to the oscillator control system.
The amplitude compensations is only applicable when XOSC_HF is running in low power mode.
Figure 6-37. OSCCFG Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
R-0h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
PER_M
PER_E
R-0h
R/W-0h
R/W-0h
Table 6-41. OSCCFG Register Field Descriptions
Bit
Field
Type
Reset
Description
31-8
RESERVED
R
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
7-3
PER_M
R/W
0h
Number of 32 KHz clocks between oscillator amplitude calibrations.
When this counter expires, an oscillator amplitude compensation is
triggered immediately in Active mode. When this counter expires in
Powerdown mode an internal flag is set such that the amplitude
compensation is postponed until the next recharge occurs.
The Period will effectively be a 16 bit value coded in a 5 bit mantissa
and 3 bit exponent
PERIOD=(PER_M*16+15)*2
PER_E
This field sets the mantissa
Note: Oscillator amplitude calibration is turned of when both this
bitfield and PER_E are set to 0
2-0
PER_E
R/W
0h
Number of 32 KHz clocks between oscillator amplitude calibrations.
When this counter expires, an oscillator amplitude compensation is
triggered immediately in Active mode. When this counter expires in
Powerdown mode an internal flag is set such that the amplitude
compensation is postponed until the next recharge occurs.
The Period will effectively be a 16 bit value coded in a 5 bit mantissa
and 3 bit exponent
PERIOD=(PER_M*16+15)*2
PER_E
This field sets the exponent
Note: Oscillator amplitude calibration is turned of when both PER_M
and this bitfield are set to 0
470
Power, Reset, and Clock Management
SWCU117C – February 2015 – Revised September 2015
Copyright © 2015, Texas Instruments Incorporated