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5 - Peripherals
If the low byte is read again, the actual value of the low byte of the counter can be read. To
benefit from the latching feature, it is necessary to read the high byte first. Conversely, reading
the high byte one more time will always yield the same value as before: a read of the high byte
must be followed by a read or the low byte.
This mechanism works identically for the CLR and the ACLR registers.
5.5.2.2 Resetting the free running counter
The free-running counter is actually a read-only register. However, it is possible to reset it by
writing any value to the low byte of either CLR or ACLR (the value written is irrelevant). It is im-
portant to note that when reset, the counter is not set to zero, but FFFCh (or -4). This must be
taken into account in the timing calculations.
The hardware reset also resets the timer to this value.
05-timrs
To make a software reset of the free running counter
Any writting access to the
low byte of the free running
counter or alternate free
running counter
free running counter = #FFFCh **
CC0 = 0
CC1 = 0
prescaler = 1/4*
* except CC0 & CC1, the other bits of the control register 2 are not affected
Reset
state
** the TOF flag goes high at the FFFFh - 0000h transition of the counter, that
is to say 4 timer clock pulses after resetting the free running counter.