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5 - Peripherals
05-intof
The interrupt service routine must clear the TOF bit before returning, using the sequence de-
scribed above. No automatic clearing is performed by the interrupt service mechanism.
5.5.3 Input capture operation
The counter, as discussed above, can be read on-the-fly by the program. This is not what the
capture feature means here.
Note before continuing: each 16-bit timer has two capture channels, 1 and 2. In the following
text, the letter i in the register names must be replaced by 1 or 2 accordingly.
The capture feature is a mechanism that takes a snapshot of the counter value at the time of
the transition of an external signal applied to a pin. The capture mode is always enabled; the
ICAPipin is shared with a parallel input-output port pin, and that port must be configured with
the corresponding pin as an input to be able to use the capture input.
The IEDGi bit in the Timer Control Register 1 selects either the rising or the falling edge of the
ICAPi pin as the active transition. When the transition occurs, the ICiHR-ICiLR pair contains
the value of the counter at the time of the transition, plus one.
The capture event also sets the ICFi bit in the TSR register, and that bit can produce an inter-
rupt request if the ICIE mask bit in the TCR1 register is set.
TOF interrupt mechanism
TOF
FFFFh - 0000h (counter)
Timer status register (TSR)
I
Condition code
register (CCR)
TOIE
Timer control register 1 (TCR1)
Timer overflow
interrupt to the core
TOIE : Timer overflow enable bit (bit 7 of TCR1)
TOF : Timer overflow bit
(bit 5 of TSR)
I
: Global interrupt enable bit (bit 3 of CCR)
