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5 - Peripherals
The input capture event, corresponding to the leading edge, sets the ICF1 bit of TASR. This
can trigger an interrupt if the ICIE mask bit is set. It must then be reset by software as
explained above.
The output compare 2 event, corresponding to the trailing edge, sets the OCF2 bit of TASR.
This can trigger an interrupt if the OCIE mask bit is set. It must then be reset by software as
explained above.
The OCF1 bit is never set in this mode. This allows the interrupt requests generated by these
two events to be separately enabled or disabled.
5.5.6 Pulse-Width Modulation mode
Two output compare circuits of the same timer are involved simultaneously in Pulse-Width
Modulation mode. This mode is selected by setting the PWM bit of the TACR2 register (or
TBCR2 for Timer B). The PWM mode and the OPM mode are exclusive; if both selection bits
are set at the same time, OPM mode is overridden by PWM mode.
In this mode, no external event resets the free-running timer; instead, the second compare cir-
cuit is used. Output Compare register 2 should be set to the value of the repetition period, con-
verted in timer ticks, minus 4. Each time the free-running timer matches the Output Compare
2 register, the same events occur as an the input capture occurs in One Pulse Mode: output
pin OCMP1_A is toggled, and the free-running counter is reset to FFFCh. Later, a successful
match with the value in the TAOC1R register toggles the output back.