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5 - Peripherals
The TAOC1HR-TAOC1LR pair is a 16 bit register whose value is continuously compared to
the free-running counter. If the compare function is not used, it can be used for general
purpose storage.
When the match occurs, the OCF1 flag is set in the TASR register. This bit can only be reset
by the following sequence: a read of TASR, then an access (read or write) to TAOC1LR.
If the OCIE bit in the TACR1 register is set, this event triggers an interrupt request. The
OCF1 bit is not cleared automatically, and must be cleared by the program as said above.
If the OC1E bit is set in the TACR2 register, the OCMP1_A pin is driven by Timer A. When
the OCF1 bit is set, this copies the level of the OLVL1 bit of the TACR1 register to the pin.
The FOLV1 bit, when set, switches the timer into a mode where the output pin constantly
reflects the state of the OLVL1 bit. The FOLV1 bit can only be set by software; to reset it, it
is necessary to perform a hardware reset.
5.5.5 One-pulse mode
The input capture and output compare features are intermingled in One Pulse Mode. This
mode is selected by setting the OPM bit in the TACR2 register (or TBCR2 for Timer B).
In this mode, an active edge on the ICAP1_A pin toggles the OCMP1_A output pin, then, after
a predefined delay, this pin is toggled back to its initial level. This is the numeric equivalent of
a one-shot multivibrator.
The settings for this mode are performed as follows:
Set the TAOC1HR-TAOC1LR register pair to the number of ticks corresponding to the delay
(this number depends on the clock frequency), minus 4.
Set the OLVL2 bit of the TACR1 register to the state required for the output pin for the
duration of the pulse, and OLVL1 of TACR1 to the complement of this state to terminate the
pulse.
Set the IEDG1 bit of TACR1 for the desired active edge on the input (0 for falling edge, 1 for
rising edge).
Set the OPM bit of TACR2 to enable the one-pulse mode.
Set the OC1E bit of TACR2 to enable the output pin.