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9 - A Carrier-current System for domestIc Remote Control
The features of the 72251 are used as follows:
The first timer is set to PWM mode. It is configured to generate a pulse on the OCMP1_A
output, that is the alternate function of the PB1 pin. The repetition period is set to exactly 1/6
of a power line cycle, and the duration of the pulse is set to 1 ms.
As specified in the ST72251 datasheet, when in PW M mode, a timer cannot generate com-
pare interrupts. However, Timer A has a special feature, that is, a Compare 2 event makes be-
lieve a Capture 1 occurred. This application takes advantage of this fact to produce an inter-
rupt request once for each period of the counter (that is six times for each power line cycle). To
allow this, the interrupt mask bit for the capture events is set.
The sine voltage from the second wire of the line (the first one being already connected to
V
SS
) is used to generate a square wave that is fed to the P B2 input actually used as the
second capture input of Timer A (ICAP2_A). So a capture of the value of the free-running timer
is performed once at each positive to negative zero-crossing of the line voltage, that is, once
per cycle. Since the capture interrupt mask is set, as said above, the Capture 2 events also
produce an interrupt request. Which event produced the request is distinguished in the inter-
rupt service routine by testing two bits, ICF1 and ICF2 in the Timer Status Register (TSRA).
The external circuit that supplies the RF energy to the power line is gated to control the times
the carrier is present. This is done using the PB1 pin that is used as the Output Compare of
Timer A (OCMP1_A). This is configured by the Output Compare Enable bit of Timer Control
Register 2 (OC1E of register TACR2) that is set to 1.
Thus configured, the timer would produce a continuous burst of 1 ms pulses. To modulate
these pulses according to the X-10 standard, the OLVL1 bit in register TACR1 is alternatively
set to one or zero to send a pulse, or not to send it. This bit sets the level that is output on
Compare 1 events. Since the OLV L2 bit sets the level that is output on Compare 2 events
(wh en the time r is in P W M m o de ), a nd t his b it is pe rm an en tly se t to zer o, t he o ut pu t
OCMP1_A either remains low, or is pulsed high, according to the state of OLVL1.
The pulses must be sent in phase with the line voltage. To obtain this, a phase-locked loop
scheme is used.
On the power line zero-crossing interrupt, the value of the free-running counter of the timer is
captured, and an interrupt request is generated. The interrupt service routine tests this value.
The aim is that it be equal to a reference value; actually, it will be either greater (ahead of time)
or smaller (behind time). A fraction of the difference between the actual and target values is
added to the reference period, and the sum is written to the Compare 2 register, thus altering
the repetition rate of the timer. This scheme is that of a closed-loop system, that stabilizes the
frequency to six times the line frequency, and the phase, so that the start of the pulse will co-
incide exactly with the zero-crossing, as required by the X-10 standard.