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5 - Peripherals
05-pulse
The input capture event both toggles the output and resets the free-running counter to FFFCh,
and a successful match with the value in the register TAOC1R toggles the output back. This is
why the compare register should be set to the calculated value minus 4.
The leading and trailing edges of the pulse can generate interrupts if desired:
One pulse mode and corresponding interrupt mechanism:
diagram for timer A
Interrupt to
the core
Input
capture 1
pin
Free running counter
16 bit output compare register
TAOC1HR, TAOC1LR
16
16
Compare
loaded with the duration
of the pulse
OCIE
Timer A control
register 1 (TACR1)
OLVL1
OLVL2
Configuration of the
input capture pin
(see the input
capture mode
diagram)
Clk
latch
Clk
latch
Configuration of
the output compare pin
(see the output compare
mode diagram)
ICIE
ICF1
OCF2
I
Condition code
register (CCR)
Timer A status
register (TASR)
Output
compare 1
pin
FFFCh
OPM
Timer A control
register 2 (TACR2)