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5 - Peripherals
The clearing of ICFi is done by a sequence similar to that described for the TOF bit:
Read the TSR register, and
Either read or write the ICiLR register.
Only the ICIE flag is common to both channels. Thus, if both channels are used simultane-
ously, on interrupt, the TSR register must be read to determine whether the ICF1 or the ICF2
bit is set (or both). The ICFi capture flag bit(s) must be cleared by the interrupt service routine
since no automatic clearing mechanism is provided.
The following table summarizes the registers and the bits involved.
Timer A:
Timer B:
The diagram below represents the timer A capture channel 1; the reader can transpose it for
the other channel or the other timer by substituting the register, bit and pin names as in the
table above.
Channel 1
Channel 2
Function
TAIC1HR & TAIC1LR TAIC2HR & TAIC2LR
Input capture registers
(16-bit, read only access)
ICAP1_A
PB0 on ST72251
PF6 on ST72311
ICAP2_A
PB2 on ST72251
doesn’t exist on ST72311
Input capture pin
ICF1
ICF2
Capture event flag in TASR
IEDG1 or TACR1
IEDG2 of TACR2
Capture Input Edge Selector.
ICIE
Common Interrupt Mask Flag in TACR1
Channel 1
Channel 2
Function
TBIC1HR & TBIC1LR TBIC2HR & TBIC2LR
Input capture registers
(16-bit, read only access)
ICAP1_B
PC0 on ST72251
PC3 on ST72311
ICAP2_B
PC3 on ST72251
PC2 on ST72311
Input capture pin
ICF1
ICF2
Capture event flag in TBSR
IEDG1 or TBCR1
IEDG2 of TBCR2
Capture Input Edge Selector.
ICIE
Common Interrupt Mask Flag in TBCR1