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5 - Peripherals
With another core clock, we would get different values. The values in bold are the most com-
monly used. Please note that they are not exact; however, asynchronous serial transmission
is by nature tolerant of bit rate errors of up to 4%. The error here is only 0.16%.
The division ratio is selected by bits in the Baud Rate Register, with two bits for the prescaler
value, then three bits for the receive divisor, and three more bits for the transmit divisor.
If no combination of the core clock and the division ratio provided by the BRR fits the your re-
quirements, you can specify a value between 1 and 255 as a prescaler for the receiver by
writing that value in the Extended Receiver Prescaler Register. The core clock is then divided
by 16, and by this division ratio. If the ERPR is set to zero, then the selections of the BRR
above apply.
Similarly, the transmitter bit rate can be fine-tuned using the Extended Transmit Prescaler
Register.
5.8.2 Send and receive mechanism
The data to be sent and the data that is received are both put in the Data Register. When this
register is written, it starts the transmit process. When a word is received, it is copied to that
register where it can be read.
The word length is set in the Control Register 1 by the M bit. If the M bit is cleared, the word
length is 8 bits; otherwise, it is 9 bits. The ninth bit, when received, is copied to the R8 bit of
that same register. To transmit a 9-bit word, the first 8 bits are taken from the Data Register
(least-significant bit first) and the value of the T8 bit of the CR1 register is used as the ninth bit.
No automatic parity generation or checking is provided. If needed, parity may be calculated by
software, then copied to either bit 7 of the byte to send, if the word length is 7 bits plus parity,
or to bit T8, if the word length is 8 bits plus parity.
The serial transmission is straightforward: if the transmit shift register is empty, the data byte
written to the Transmit Data Register is copied to it. The serial sending process starts then, by
sending a zero bit (the start bit), then the byte to transmit, LSB first, then the T8 bit if the word
length is set to 9 bits, then a one bit (the stop bit). The transmission is then complete.
As soon as the Transmit Data Register is empty, the TDRE bit in the S tatus Register is set.
When the transmission is complete (when the shift register is empty), the TC bit is set. These
bits are cleared by first reading the SCISR register then accessing the SCITDR register.
The SCITDR acts as a buffer to allow a continuous data flow on the serial line, by reacting to
the interrupts that are generated when TDRE is set. This allows the core to supply the next
character in the time needed to transmit a character (about 500 µs at 19200 bits per second).