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5 - Peripherals
5.8.3 Status register
The Status Register includes the following bits that show the current status of the SCI:
The TDRE and TC bits, if set, indicate that a new character may be supplied to continue the
transmission. The difference between these bits comes from the fact the SCI has a buffer
before the transmit shift register. The TDRE bit indicates that the buffer is empty, but the shift
register may not be empty. TC indicates that the shift register is empty, which also implies
that the buffer is empty. Depending on what you want to do, either or both of these bits may
be taken into account: TDRE indicates that the next character to send may now be supplied;
TC indicates that the last character is sent.
The RDRF bit indicates that a character has been received.
The IDLE bit goes to one when a full character time or more has elapsed since the last
character was received, indicating that the incoming character flow is suspended.
The next three bits show that an error condition has been detected. The OR bit (OverRun)
indicates that the last-but-one character that remained unread in the Data Register has been
overwritten by the last character received: it is thus lost. Each bit is sampled three times, if
the three sample are not the same, the NF bit (Noise Flag) is set and the bit value is
determined according to the 2 to 1 majority rule. The FE bit (Framing Error) indicates that a
proper stop bit was not present at the end of the character. The interpretation of these error
conditions is not necessarily pertinent; however, the occurrence of any of these errors tends
to mean there is a transmission problem and that the data transfer is not reliable. The
character received in the Data Register is probably incorrect.
There is one case where a Framing Error is detected and where this condition is expected. It
is the case of a B reak condition. A Break is a state of the line where it is in its active state
(“Mark”, or zero) for at least one character period. This may indicate that the line has been dis-
connected. It is also possible that the transmitter puts a normally connected line in Break con-
dition. This may be used to signal a particular event and it is up to the system designer to de-
cide which event.
5.8.4 Control Register 2
The Control Register 2 contains the following bits:
TIE and TCIE, if set, enable an interrupt request when the TDRE or TC bits in the Status
Register are set, respectively.
RIE, if set, enables an interrupt when the RDRF bit in the Status Register is set.
ILIE, if set, enables an interrupt when the IDLE bit in the Status Register is set.
TE and RE enable the transmitter and the receiver respectively, and change the appropriate
port pins to Serial Output and Serial Input.