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5 - Peripherals
ister. When this bit is set, no interrupts are generated. However, the interrupt requests are not
forgotten; they will be processed as soon as the I bit is reset.
5.2.4 TRAP instruction
In addition to the hardware sources, a special instruction, TRAP, produces the same effect as
an externally generated interrupt request, but under program control. Strange as this may
seems (interrupts are provided to handle unexpected events, or at least, events for which the
time of occurrence is not known), the TRAP instruction uses of the interrupt mechanism within
the regular execution of the main program.
The trap instruction triggers interrupt processing regardless of the state of the I bit in the Con-
dition Code register.
An example of the use of the TRAP instruction is the real-time debugger. When the user sets
a breakpoint somewhere in the program, the debugger replaces the instruction at which the
execution must stop with a TRAP instruction. The interrupt thus generated is processed by
displaying on the screen the state of the microcontroller at that precise time. However, other
uses of this instruction may be found as well.
5.2.5 Interrupt mechanism
5.2.5.1 Saving the interrupted program state
When the interrupt request triggers an interrupt, the first task of the core is to save its current
state so as it will be able to restore it after the interrupt processing is finished. This is done by
pushing all the core registers to the stack, namely the Program Counter, the X-register, the
Accumulator and the Condition Code Register. It should be noted that the Y register is not
saved, for compatibility with the standard instruction set which the ST7 adheres to. If needed,
the Y register may be pushed explicitly to the stack at the beginning of the interrupt service
routine.
At this point (and with the restriction above mentioned about the Y register), the interrupt
service routine may execute freely. The status of the interrupted program is known and can be
restored when needed.
To protect the interrupt service routine from other interrupt requests, the I bit of the Condition
Code Register is then automatically set by hardware.
5.2.5.2 Interrupt service routine
When the processor has granted the interrupt request, and read the interrupt vector, it starts
executing the interrupt service routine. This routine is merely a segment of program, written
with exactly the same ease and constraints as the main program. It can be written using the
same language and tools, or in any other language.