RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
1070
5-3
5.2 IMPLEMENTATION
A representation of the HDLC process is shown in Figure 5-3. The events are numbered in order of occurrence from one to
four.
1. The beginning flag is transmitted. The receiver sees the flag and now becomes aligned with the transmitter. Both the
receive and the transmitter FCS registers are preset to FFFFh.
2. The information field is transmitted. The data is also run through the FCS register before zero insertion. At the receive
end, after the zero deletion algorithm, the data is presented to the user and then run through the FCS register.
3. The FCS is inverted and then transmitted. The transmitted FCS is passed through the receiver's FCS register. The shift
register will contain 1111000010111000 if the frame has been received correctly.
4. The ending flag is transmitted.
The signal timing is illustrated in Figure 5-4.
FLAG
FLAG
FLAG
FLAG
A C I
A C I
ZERO DELETE
ZERO INSERT
PREMULTIPLY BY x
16
PREMULTIPLY BY x
16
FCS REGISTER
FCS REGISTER
1111000010111000
ZERO DELETE
ZERO INSERT
RECEIVING LINK STATION
BEGIN
END
TRANSMITTING LINK STATION
(1) TRANSMIT FLAGS (4)
(2) TRANSMIT FLAGS
(3) TRANSMIT FCS
MESSAGE POLYNOMIAL
MESSAGE POLYNOMIAL
GENERATING POLYNOMIAL
PRESET TO ALL 1S
GENERATING POLYNOMIAL
PRESET TO ALL 1S
CONTENTS OF SHIFT REGISTER
AT END OF FRAME.
WHEN ENTIRE FRAME TRANSMITTED, FCS
REGISTER CONTAINS REMAINDER OF
SHIFT REGISTER CONTAINS ABOVE VALUE
AT END OF FRAME IF TRANSMISSION IS
ERROR FREE.
MESSAGE POLYNOMIAL
GENERATION POLYNOMIAL
THE QUOTIENT IS DISCARDED.
INVERT
1070F5-3 HDLC Process
Figure 5-3. HDLC Process
Summary of Contents for RFX144V24-S23
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