RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
5-2
1070
Information Field
The modem treats the address field, the control field, and any other transmitted data, except for the flags and the Frame
Check Sequence, as the information field. The information field does not have a set length; however, this field follows the
SDLC protocol in being in the format of eight bit bytes.
Zero Insertion
Since flags mark the beginning and ending of a frame, some method must be implemented to inhibit or alter the transmission
of data that appear as flags. The method used is called “zero insertion”. HDLC procedures require that a zero be transmitted
following any succession of five continuous ones. This includes all data in the address, control, information and Frame Check
Sequence fields. Use of zero insertion denies any pattern of 01111110 to ever be transmitted between beginning and ending
flags.
Zero Deletion
When transmitting flags, zero insertion is disabled. During reception of data, after testing for flag recognition, the receiver
removes a zero that immediately follows five continuous ones. This is termed “zero deletion”. A one that follows five
continuous ones signifies either a frame abort (i.e., at least seven ones with no zero insertion) or a flag (i.e., 01111110). The
sixth one is, therefore, not removed.
Frame Check Sequence (FCS)
The purpose of the Frame Check Sequence (FCS) is to give a shorthand representation of the entire transmitted information
field and to compare it to the identically generated shorthand representation of the received sequence. If any difference
occurs, the received frame was in error and should be re-transmitted.
The FCS computation is done on all fields within the frame but does not include the flags. Cyclic Redundancy Check (CRC)
is the method used. The polynomial is specified in CCITT T.30 and X.25 as follows:
x
16
+ x
12
+ x
5
+ 1
The polynomial is implemented as shown in Figure 5-2.
The FCS is sent as two bytes of data immediately preceding the ending flag of the frame. The FCS register is first preset to
all binary ones. The register is then modified by shifting in the data (no flags) contained in the address, control, and
information fields. Following the last bit of data, the ones complement of the FCS register is transmitted as the 16-bit FCS.
The FCS is transmitted with the highest order bit (x15) first.
INPUT
XOR
XOR
XOR
X
0
X
1
X
2
X
3
X
4
X
12
X
13
X
14
X
15
X
5
X
6
X
7
X
8
X
9
X
10
X
11
1070F5-2 CRC
Figure 5-2. CRC Polynomial Implementation
5.1.2 Frame Abortion, Frame Idle, And Time Fill
Frame abortion prematurely finishes transmission of a frame. This occurs by sending at least seven consecutive ones with
no zero insertion. This abort pattern terminates a frame immediately and does not require a FCS or an ending flag.
An abort pattern followed by a minimum of eight additional consecutive ones idles the data link. Thus, seven to fourteen
ones establish the abort pattern; fifteen or more ones constitute an idle pattern.
Interframe time fill is accomplished by transmitting continuous flags without zero-sharing between flags. Therefore, the
transmitter must be capable of sending multiple flags to maintain the active state in the receiver if any time fill is required.
Summary of Contents for RFX144V24-S23
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