RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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4.1.4 DSP RAM Write Procedure
The RAM write procedure is a 16-bit transfer from interface memory to DSP RAM allowing the transfer of X RAM data or Y
RAM data to occur each baud data, or sample time (Figure 4-1).
1. Before writing to DSP interface memory, reset ACC1 and/or ACC2 to a 0; then read YDAL1 and/or YDAL2 to reset B1A
and/or B2A, respectively.
2. For main RAM access, write the RAM address into ADD1 and AREX1 and/or ADD2 and AREX2, reset SBRAMx, then
set CR1 and IO1 and/or CR2, and IO2 to the chosen values. For single bank RAM access, write the address to
SBADxM and SBADxL and set the SBRAMx bit.
3. Set WRT1 and/or WRT2 to a 1 to inform the DSP that a RAM write will occur when ACC1 and/or ACC2 is set to a 1.
4. Write the desired data into the interface memory RAM Data registers YDAL1 and YDAM1 and/or YDAL2 and YDAM2.
5. Set ACC1 and/or ACC2 to a 1 to signal the DSP to perform the RAM write.
6. The DSP sets B1A and/or B2A after transferring the contents of the interface memory registers into RAM.
7. If B1I1E or B2I1E is a 1, ~IRQ1 is also asserted and B1IA and/or B2IA is set to a 1 when B1A and/or B2A is set to a 1
by the DSP.
8. If B1I2E and/or B2I2E is a 1, the DSP asserts ~IRQ2 when B1A and/or B2A is a 1. B1I2E and B2I2E have no effect on
B1IA and B2IA, respectively.
9. Clear B1IA and/or B2IA by writing into YDAL1 and/or YDAL2, which causes ~IRQ1 to return high if no other interrupt
requests are pending.
10. ~IRQ2 returns high only when B1A and/or B2A are reset to 0.
Summary of Contents for RFX144V24-S23
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