RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
1070
3-11
Table 3-1. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Location
Default
Name/Description
FR1
08:5
–
Frequency No. 1. The modem sets status bit FR1 to a 1 when energy above tone detector 1's turn-on
threshold is detected. The default detection range = 2100 Hz ± 25 Hz for 9600 Hz sample rate. The FR1
tone detector sample rate is either 4000/8000 Hz in Voice Codec Mode (CONF = 90h or 98h) and Audio
Codec Mode (CONF = 92h or 94h), 8000 Hz in Audio Mode (CONF = 82h or 86h) and 4000 Hz in
Speakerphone Mode (CONF = 91h). Control bit TND8K selects 8000 Hz or 4000 Hz sample rate. The
FR1 detector must be reprogrammed for 4000 Hz and 8000 Hz..
FR2
08:6
–
Frequency No. 2. The modem sets status bit FR2 to a 1 when energy above tone detector 2's turn-on
threshold is detected. The default detection range = 1100 Hz ± 30 Hz for 9600 Hz sample rate. The FR2
tone detector sample rate is 4000 Hz/8000 Hz in Voice Codec Mode (CONF = 90h or 98h) and Audio
Codec Mode (CONF = 92h or 94h), and 8000 Hz in Audio Mode (CONF = 82h or 86h). Control bit
TND8K selects 8000 Hz or 4000 Hz sample rate. The FR2 detector must be reprogrammed for 4000 Hz
and 8000 Hz.
FR3
08:7
–
Frequency No. 3. The modem sets status bit FR3 to a 1 when energy above tone detector 3's turn-on
threshold is detected. The default detection range = 462 Hz ±14 Hz for 9600 Hz sample rate. The FR3
tone detector default sample rate is 4000 Hz/8000 Hz in Voice Codec Mode (CONF = 90h or 98h) and
Audio Codec Mode (CONF = 92h or 94h), and 8000 Hz in Audio Mode (Conf = 82h or 86h). Control bit
TND8K selects 8000 Hz or 4000 Hz sample rate. The FR3 detector must be reprogrammed for 4000 Hz
and 8000 Hz.
FRx
17:1
–
Frequency No. 1, 2, or 3. Status bit FRx is set by the modem if FR1, FR2, or FR3 is set. FRx is reset
by the modem if FR1, FR2, and FR3 are reset.
FSK7E
08:2
–
FSK FLAG (7E) Detected. The modem sets status bit FSK7E to a 1 when FSK flags have been
detected in a high speed receiver mode. FSK7E is valid after bit FSKFLS transitions from 1 to 0. FSK7E
is not valid in V.27 ter short train modes.
FSKFLS
0E:7
0
FSK FLAG (7E) Search. When status bit FSKFLS is a 1, the modem is searching for FSK flags in high
speed receiver modes except V.27 ter short train. This bit is reset by the modem when the FSK flag
search is completed.
GPIx
16:0-7
-
General Purpose Inputs. The modem sets/resets bits 0 -7 in the GPIx register to represent the
corresponding logic level (1 = high, 0 = low) appearing on signals GPI0 - GPI7, respectively, within 125
µs of signal transition.
GPI7 is typically connected to the DAA ring detection circuitry, and bit RI in the interface memory
represents a valid ring frequency if it is so connected.
GPOx
1B:0-7
1
General Purpose Outputs. Bits 0-7 in the GPOx register, set/reset by the host, are reflected by logic
level outputs (1 = high, 0 = low) appearing on signals GPO0 - GPO7, respectively, within 125 µs of bit
transition.
HDLC
07:0
0
HDLC Mode. When control bit HDLC is a 1 and the PDM bit is a 1, the modem performs HDLC framing
in parallel data mode. When the HDLC bit is a 0 or the PDM bit is a 0, the modem does not perform
HDLC framing. In data modes, changing the value of the HDLC bit requires setting the SETUP bit to
become active.
In the Voice Codec mode (CONF = 90h or 98h), error correction is enabled (HDLC = 1) or disabled
(HDLC = 0). Setting the SETUP bit is not required.
HPFEN
0D:2
0
High Pass Filter Enable. When control bit HPFEN is a 1, the Pre-AGC high pass filter is enabled in the
receive path.
IO1
05:3
0
Input/Output RAM 1 Select. When control bit IO1 is a 1, ADD1 addresses IO RAM. When IO1 is a 0,
ADD1 addresses either coefficient or data RAM depending on the state of the CR1 bit. This bit must be
set according to the desired RAM address. (See Table 4-1).
IO2
15:3
0
Input/Output RAM 2 Select. When control bit IO2 is a 1, ADD2 addresses IO RAM. When IO2 is a 0,
ADD2 addresses either coefficient or data RAM depending on the state of the CR2 bit. This bit must be
set according to the desired RAM address. (See Table 4-1).
Summary of Contents for RFX144V24-S23
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