RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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5-9
Receiver Example
The steps to perform a typical HDLC reception are:
1. Set the modem configuration to the desired speed for receiving, enable HDLC, and parallel data mode.
2. Perform a dummy read of DBUFF to reset B2A.
3. Wait until the modem has properly configured.
4. Monitor, through interrupts, the EOF, ABIDL, and B2A bits in the interface memory.
5. Wait for an interrupt. If it is caused by B2A being set, read the data in DBUFF. This indicates that the first byte of the
first frame is ready for host reading. If the interrupt is caused by EOF being set, check CRC to determine if the current
frame is in error and reset EOF. If the interrupt is caused by ABIDL, the modem is receiving the abort/idle sequence.
The current frame that was aborted is invalid. The modem does not set the CRC bit or the EOF bit in this case since no
FCS checking is done.
6. Continue waiting for interrupts and take appropriate action when the interrupts are received.
Summary of Contents for RFX144V24-S23
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