RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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Table 2-3. MDP Hardware Interface Signal Definitions (Cont'd)
Label
I/O Type
Signal Name/Description
V.24 SERIAL INTERFACE
These pins provide timing, data, and control signals for implementing a ITU-T Recommendation V.24 compatible
serial interface. These signals are TTL compatible in order to drive the short wire lengths and circuits normally
found within stand-alone modem enclosures or equipment cabinets. For driving longer cables, these signals can
be easily converted to EIA/TIA-232-E voltage levels.
TXD
IA
Transmit Data. The modem obtains serial data to be transmitted from the local DTE on the Transmit Data
(TXD) input in serial data mode (PDM bit = 0), or from the interface memory Transmit Data Register (DBUFF) in
parallel data mode (PDM bit = 1).
RXD
OA
Received Data. The modem presents received serial data to the local DTE on the Received Data (RXD) output
and to the interface memory Receive Data Register (DBUFF) in parallel data mode.
~RTS
IA
Request to Send. The active low ~RTS input allows the modem to transmit data present at TXD in the serial
data mode (PDM bit = 0), or in DBUFF in the parallel data mode (PDM bit = 1), when ~CTS becomes active.
The ~RTS hardware control input is logically ORed with the RTSP bit (Table 3-1) by the modem to form the
resultant control signal.
~CTS
OA
Clear To Send. ~CTS active indicates to the local DTE that the training sequence has been completed and any
data present at the TXD input in the serial data mode or in DBUFF in the parallel data mode will be transmitted.
~CTS response times from ~RTS on are shown in Table 1-3.
The ~CTS hardware status output parallels the operation of the CTSP bit (Table 3-1).
~RLSD
OA
Received Line Signal Detector. For V.17, V.33, V.29, and V.27 ter; ~RLSD goes active at the end of the
training sequence. If energy is above the turn-on threshold and training is not detected, the ~RLSD off-to-on
response time is 816 baud times for V.17/V.33, V.29, and V.27 ter long train; 492 baud times for V.17/V.33; and
486 baud times for V.27 ter short train. The ~RLSD on-to-off time is 40 ± 5 ms for V.17/V.33, 35 ± 5 ms for V.29
or 11.6 ± 5 ms for V.27 ter. The ~RLSD on-to-off time ensures that all valid data bits have appeared on RXD.
The ~RLSD programmable threshold levels default to -43 dBm for off-to-on and to -48 dBm for on-to-off. A
minimum hysteresis of 2 dBm exists between the actual off-to-on and on-to-off transition levels. The threshold
level and hysteresis are measured with an unmodulated 2100 Hz tone applied to the Receiver Analog (RXA)
input. Note that performance may be degraded when the received signal level is less than -43 dBm.
DCLK
OA
Data Clock. The modem outputs a synchronous Data Clock (DCLK) for USRT timing. The DCLK frequency is
the data rate (±0.01%) with a duty cycle of 50 ±1%. The DCLK low-to-high transitions coincide with the center of
the data bits. Transmit Data (TXD) must be stable during the one microsecond period immediately preceding the
rising edge of DCLK and following the rising edge of DCLK.
AUXILIARY SIGNALS
~EN85
IA
Enable 85 Bus. The ~EN85 input selects the modem microprocessor bus compatibility. When ~EN85 is low,
the modem can interface directly to an 8085 compatible microprocessor bus using ~READ and ~WRITE. When
~EN85 is high, the modem can interface directly to a 6500 compatible microprocessor bus using ø2 and R/~W.
In the 6500 configuration, the ~READ input becomes ø2 and the ~WRITE input becomes R/~W. This selection
is performed only during initialization, i.e., when ~POR is asserted.
XCLK
OD
XCLK Output. XCLK is a 49.92 MHz or 53.76 MHz square wave output derived from XTLI.
YCLK
OD
YCLK Output. YCLK is a 24.96 MHz or 26.88 MHz square wave output derived from XTLI (XTLI / 2).
~SLEEP
IA
Sleep. A low on the ~SLEEP input causes the analog codec circuit to enter Sleep Mode; a high wakes up the
analog codec circuit. The ~SLEEP input should be connected to the GPO0 output pin. Entry into the modem
Sleep Mode is controlled by writing a 0 into the Sleep Mode Enable RAM parameter (see Table 4-1).
Summary of Contents for RFX144V24-S23
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