Rockwell RFX144V24-S23, Designer'S Manual

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RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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Table 3-1. Interface Memory Bit Definitions (Cont'd)
Mnemonic Location Default Name/Description
ITADRS 0A:0-4 0 Interrupt Address. These 5 bits specify the register upon which the programmable interrupt and
ITBMSK will take effect. The address of the byte on which the modem asserts ~IRQ1 on a bit or bits in
that byte is:
Host Register ITADRS Host Register ITADRS
(Hex) (Hex) (Hex) (Hex)
00 00 10 08
01 10 11 18
02 01 12 09
03 11 13 19
04 02 14 0A
05 12 15 1A
06 03 16 0B
07 13 17 1B
08 04 18 0C
09 14 19 1C
0A 05 1A 0D
0B 15 1B 1D
0C 06 1C 0E
0D 16 1D 1E
0E 07 1E 0F
0F 17 1F 1F
ITBMSK 0B:0-7 00 Interrupt Bit Mask. This byte performs a bit mask on the register specified in ITADRS for the
programmable interrupt processing. A one in any position in ITBMSK will cause the modem to assert
~IRQ1 on the corresponding bit or bits in the register specified by ITADRS according to the ANDOR bit
and the TRIG bits if PIE is set by the host and PIREQ is reset by the host.
MICLVL 0E:0-1 01 Microphone Volume Level. In speakerphone mode, The MICLVL bits control the XIA ADC signal gain
as follows:
Bit 1 Bit 0 Gain
0 0 0 dB
0 1 6 dB
1 0 9.5 dB
1 1 12 dB
MUTEI 0E:3 0 Mute IIA ADC. In speakerphone mode, control bit MUTEI enables (MUTEI = 1) or disables (MUTEI = 0)
muting of the IIA ADC signal.
MUTEX 0E:2 1 Mute XIA ADC. In speakerphone mode, control bit MUTEX enables (MUTEX = 1) or disables (MUTEX
= 0) muting of the XIA ADC signal.
NORM 14:0 1 Normal Playback Speed. When control bit NORM is a 1 and the FAST50, FAST33, and SLOW control
bits are reset, normal playback speed is selected. NORM must be reset when another speed is
selected. (Voice Codec Mode)
OE 09:7 – Overrun Error (Parallel Mode). When set, status bit OE indicates that the receive Data Buffer
(DBUFF) was loaded with the new byte of received data before the host read the old data from DBUFF.
When reset, DBUFF was read before new receive data was loaded into DBUFF. (V.23)