RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
2-16
1070
Table 2-9. Microprocessor Interface Timing
Parameter
Symbol
Min.
Max.
Units
~CS Setup Time
TCS
0
-
ns
RSi Setup Time
TRS
10
-
ns
Data Access Time
TDA
-
45
ns
Data Hold Time
TDHR
10
-
ns
Control Hold Time
THC
10
-
ns
Write Data Setup Time
TWDS
20
-
ns
Write Data Hold Time
TDHW
10
-
ns
Phase 2 (ø2) Clock High
TP2CH
70
-
ns
Notes:
1.
~CS and ~READ must not both be active continuously.
2.
A read or write operation following a write operation must be delayed by at least 2 YCLK cycles.
3.
A read or write operation following a read operation must be delayed by at least 1 YCLK cycle.
T ON
~ RTS
~ CTS
DCLK
TXD
FIRST DATA BIT TRANSMITTED
LAST DATA BIT TRANSMITTED
TRANSMITTED ENERGY
T OFF
1070F2-5 Tx Timing
Figure 2-5. Transmitter Signal Timing
~ RLSD
DCLK
RXD
FIRST BIT RECEIVED
LAST BIT RECEIVED
RECEIVED ENERGY
1070F2-6 Rx Timing
Figure 2-6. Receiver Signal Timing
Summary of Contents for RFX144V24-S23
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