RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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The hardware ~IRQ1 pin must be monitored for interrupts. The ~IRQ1 pin will become active (go low) when the modem is
ready for a byte of data. This data should be loaded into the Data Buffer Register, DBUFF. When the ~IRQ1 returns low, the
modem is ready for the next byte of data. Alternately, ~IRQ2 can be used.
Figure 9-14 describes how to receive FSK/HDLC signals. The Interrupt-Driven Low Speed Receive routine is shown on
Figure 9-15.
After ~IRQ1 is low, the Buffer 2 Available (B2A) bit is polled to determine if the next byte must be read by the host. If B2A is
a 0, the Programmable Interrupt Request (PIREQ) bit is polled to determine if one of the programmable interrupt bits caused
the interrupt. If Abort/Idle (ABIDL) is a 1, then an abort or idle sequence is being received. If ABIDL is a 0, then a Return
from Subroutine is executed and the End of Frame bit is checked to see if it is the end of the frame. The Cyclic Redundancy
Check (CRC) bit is looked at to determine if the current frame was received correctly. Figure 9-16 shows how to re-configure
the modem to a high speed configuration. This procedure will be used again when entering phase C. Figure 9-17 describes
how to transmit the TCF or one second of zeros. Figure 9-18 describes the High Speed Message Transmission. This
procedure is similar to the Low Speed Message Transmission. The High Speed Configuration is located at Figure 9-16.
The High Speed Interrupt-Driven Transmit routine is in Figure 9-19. This is also similar to the low speed procedure.
The High Speed Message Reception procedure is illustrated in Figure 9-20. The High Speed Interrupt-Driven Receive
subroutine is in Figure 9-21. Included in the High Speed Message Reception procedure is an optional Ensure Valid Train
subroutine (Figure 9-22). This procedure is recommended to ensure that a valid training sequence is accomplished when
noise is above the RLSD turn-on threshold.
Summary of Contents for RFX144V24-S23
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