RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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5-5
5.2.1 Mode
Selection
In order to use HDLC in the modem, the host processor must:
1. Set up the modem configuration.
2. Set the parallel data mode bit (PDM).
3. Set the HDLC mode bit.
4. Set the SETUP bit.
RAM Access 1 (using ADD1) remains available while RAM Access 2 (using ADD2) is unusable in the parallel data mode.
HDLC transmission cannot be performed using the serial interface.
The format of the data input to the modem is in groups of 8-bit bytes. As in the parallel data mode, the least significant bit of
the byte is transmitted first.
5.2.2 Transmission and Reception Rate
The HDLC as implemented in the modem runs under the following transmitter and receiver modes:
V.33 and V.17
V.29
V.27 ter
V.21
V.21 with DTMF receiver
5.2.3 Transmitter and Receiver Initialization
The HDLC transmitter and receiver is initialized differently than other modes upon power-up, reconfiguration, or turning on
~RTS input or RTSP bit. Table 5-1 shows the states of the interface memory bits for HDLC initialization.
Table 5-1. Transmitter and Receiver Initialization
Parameter
Transmitter
Receiver
ABIDL
0 (Note 2)
0 (Note 2)
AEOF
0 (Note 2)
0 (Note 2)
B2A
1
Not initialized
CRC
0 (Note 1, 2)
0 (Note 2)
EOF
0 (Note 2)
0 (Note 2)
FLAG
0
0
OVRUN
0 (Note 2)
0 (Note 2)
ZEROC
0 (Note 2)
0 (Note 2, 3)
Notes:
1.
Not applicable in the transmitter.
2.
Zeroed only upon power-up; unchanged elsewhere.
3.
Not applicable in the receiver.
Summary of Contents for RFX144V24-S23
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