RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
3-10
1070
Table 3-1. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Location
Default
Name/Description
EOF
09:2
–
End of Frame. In HDLC mode, when the modem is configured as a transmitter and bit AEOF is a 0, the
EOF bit is a control bit. When AEOF is a 0, to convey to the modem that it is time to send the 16-bit FCS
and ending flag of an HDLC frame, the host must set the EOF bit after the modem has taken the last
byte of data (resides in DBUFF) of the frame (B2A sets again). EOF will then be reset by the modem
after it has recognized the setting of EOF by the host.
When the modem is configured as a transmitter and bit AEOF is a 1, EOF is a status bit. In this case,
the modem will interpret the underrun condition as the end of the frame, set EOF, and will output the 16-
bit FCS and at least one ending flag. EOF is reset whenever a flag is transmitted.
When the modem is configured as a receiver and bit AEOF is a 1, the modem has received a frame
ending flag and the CRC bit is updated. EOF must be reset by the host before receiving the ending flag
of a following frame.
EPT
07:3
1
Echo Protector Tone Enable. When control bit EPT is a 1, an unmodulated carrier is transmitted for
187.5 ms followed by 20 ms of no transmitted energy prior to the transmission of the training sequence.
When EPT is a 0, neither the echo protector tone nor the 20 ms of no energy are transmitted prior to the
transmission of the training sequence except in V.29 long train which transmits 20 ms of silence at the
beginning of training. (See status bit P1.) The setting of the EPT bit must be followed by the setting of
the SETUP bit to become active.
EQFZ
09:5
0
Equalizer Freeze. When control bit EQFZ is a 1, updating of the receiver's adaptive equalizer taps is
inhibited.
EQSV
09:6
0
Equalizer Save. When control bit EQSV is a 1, the adaptive equalizer taps are not zeroed when
reconfiguring the modem or when entering the training state. Adaptive equalizer taps are also not
updated during training. For short train only, this bit is used in conjunction with the SHTR bit.
FAST33
14:2
0
Faster by 33% Playback Speed. When control bit FAST33 is a 1 and the FAST50, SLOW, and NORM
control bits are reset, playback time is 67% of normal playback time. FAST33 must be reset when
another speed is selected. (Voice Codec Mode)
FAST50
14:3
0
Faster by 50% Playback Speed. When control bit FAST50 is a 1 and the FAST33, SLOW, and NORM
control bits are reset, playback time is 50% of normal playback time. FAST50 must be reset when
another speed is selected. (Voice Codec Mode)
FE
09:1
0
Framing Error (Parallel Mode). When set, status bit FE indicates that more than 1 in 8 characters were
received without a Stop bit in asynchronous mode. When reset, no framing error is detected. (V.23)
FED
0F:7,6
–
Fast Energy Detector. Status bits FED indicates the level of the received signal according to the
following codes:
Bit 7
Bit 6
Energy Level
0
0
No energy (idle mode)
0
1
Invalid
1
0
Above Turn-off Threshold
1
1
Above Turn-on Threshold
FLAG
09:0
–
FLAG Mode. When the modem is configured as a transmitter and status bit FLAG is a 1, the modem is
transmitting a flag sequence. When the modem is configured as a receiver and status bit FLAG is a 1,
the modem has received a flag sequence. (HDLC mode.)
Summary of Contents for RFX144V24-S23
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