Rockwell RFX144V24-S23, Designer'S Manual

Page: 22 / 198

RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
2-6 1070
Table 2-3. MDP Hardware Interface Signal Definitions
Label I/O Type Signal/Definition
OVERHEAD SIGNALS
XTLI, XTLO R, R Crystal In and Crystal Out. The modem must be connected to an external crystal circuit consisting of a third
overtone 49.92 MHz or 53.76 MHz crystal, three capacitors, an inductor, and a resistor.
~RESET ID Reset. After application of +5V power to the modem, ~RESET must be held low for at least 15 ms after the +5V
power reaches operating range. The modem is ready to use 25 ms after the low-to-high transition of ~RESET.
The reset sequence initializes the modem interface memory (Table 3-1) to default values.
~POR IA Power-On-Reset. Connect to ~RESET.
VDDn PWR Supply Voltage for DSP Circuits. Connect to VCC.
AVDD PWR Supply Voltage for IIA Digital Circuits. Connect to VCC through decoupling circuit.
VAAn PWR Supply Voltage for IIA Analog Circuits. Connect to VCC through decoupling circuit.
DGNDn GND Ground for DSP Circuits. Connect to digital ground.
DGNDAn GND Ground for IIA Digital Circuits. Connect to analog ground.
AGNDn GND Ground for IIA Analog Circuits. Connect to analog ground.
MICROPROCESSOR BUS INTERFACE
Address, data, control, and interrupt hardware interface signals allow modem connection to an 8085 or 6500
bus compatible microprocessor. With the addition of external logic, the interface can be made compatible with a
wide variety of other microprocessors, such as the 8080 or 68000.
The microprocessor interface allows a microprocessor to change modem configuration, read or write channel
and diagnostic data, and supervise modem operation by writing control bits and reading status bits.
Note that the modem should not be continuously selected for read operation. Also, read or write operations
should be delayed by at least 2 YCLK cycles from a preceding write cycle.
D0-D7 IA/OB Data Lines. Eight bidirectional data lines (D0-D7) provide parallel transfer of data between the host and the
modem. The most significant bit is D7. Data direction is controlled by the Read Enable (~READ-ø2) and Write
Enable (~WRITE-R/~W) signals.
During a read cycle, data from the DSP interface memory register is gated onto the data bus by means of three-
state drivers in the DSP. These drivers force the data lines high for a one bit, or low for a zero bit. When not
being read, the three-state drivers assume their high-impedance (off) state.
During a write cycle, data from the data bus is copied into the selected DSP interface memory register, with high
and low bus levels representing one and zero bit states, respectively.
RS0-RS4 IA Register Select Lines. The five active high Register Select inputs (RS0-RS4) address interface memory
registers within the DSP when ~CS is low. These lines are typically connected to address lines A0-A4.
When selected by ~CS low, the DSP decodes RS0 through RS4 to address one of 32 8-bit internal interface
memory registers (00-1F). The most significant address bit is RS4 while the least significant address bit is RS0.
The selected register can be read from, or written into, via the 8-bit parallel data bus (D0-D7).
~CS IA Chip Select. The active low ~CS input selects and enables the modem DSP for parallel data transfer between
the DSP and the host over the microprocessor bus.