RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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3-13
Table 3-1. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Location
Default
Name/Description
OTS
1C:5
–
On-Time Satisfied. When configured as an DTMF receiver, the modem sets status bit OTS to 1 after
the DTMF on-time criteria is satisfied. This bit is reset by the modem after DTMFD is set to a 1 or if the
received signal fails to satisfy the DTMF off-time criteria.
OTSC
17:5
0
On-Time Satisfied Copy. In DTMF modes, OTSC is a copy of the OTS bit for programmable interrupt
control.
OVRUN
09:7
–
Overrun/Underrun. In HDLC mode, when configured as a transmitter and control bit AEOF is a 0, the
modem sets status bit OVRUN to a 1 if a transmit underrun condition occurs. If the host does not load in
a new byte of data in DBUFF within eight bit times of loading the previous byte into DBUFF, OVRUN
and ABIDL bits will be set. The modem will then automatically send eight continuous ones. The
transmission of these ones will continue until the host resets ABIDL. The modem will then finish sending
the current group of eight ones and will either start sending another frame (if B2A is a 0) or will transmit
continuous flags. The modem will reset OVRUN every time it sets B2A. If AEOF is a 1, OVRUN is
disabled.
When configured as a receiver, the modem sets the OVRUN bit to a 1 if a receive overrun condition
occurs. To detect the next overrun condition, the host must reset this bit.
P1
0C:1
–
P1 Sequence. When the modem is configured as a high speed transmitter, status bit P1 = 1 indicates
the P1 sequence is being sent. When P1 = 0, the P1 sequence is not being sent. The P1 sequence is
an echo protection tone.
When the modem is configured as a receiver, the P1 bit has no meaning.
P2
0C:2
–
P2 Sequence. When the modem is configured as a high speed transmitter, status bit P2 = 1 indicates
the P2 sequence is being sent. When P2 = 0, the P2 sequence is not being sent.
When the modem is configured as a high speed receiver, status bit P2 = 1 indicates the search for the
P2 to PN transition is occurring. When P2 = 0, the P2 to PN transition search is not occurring.
PARSL
14:4,5
00
Parity Select. In V.23 mode, control bits PARSL select the method by which parity is generated and
checked during asynchronous parallel data mode. The options are:
Bit 5
Bit 4
Parity Selected
0
0
Mark Parity
0
1
Space Parity
1
0
Even Parity
1
1
Odd Parity
PDEQZ
08:0
0
Programmable Digital Equalizer. When the host has configured the modem as a high speed receiver
or transmitter and has set control bit PDEQZ, the programmable digital equalizer is enabled. When
control bit PDEQZ is a 0, the programmable digital equalizer is disabled. The programmable digital
equalizer defaults to a Japanese 2 link delay equalizer.
Summary of Contents for RFX144V24-S23
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