Rockwell RFX144V24-S23 Designer'S Manual Download Page 34

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RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide

2-18

1070

P2-4

P2-3

P2-2

P2-5

P2-9

P2-1

EYEXY

EYESYNC

~EYECLK

1 2

9 8

3 4

+5V

+5VA

6.04K

3.92K

20.0K

80.6K

+5VA

+5V

+5VA

+5V

6.04K

3.92K

20.0K

80.6K

+5V

CLR CLK

ENP

ENT

RCO

74HC161

LOAD

ENP

ENT

RCO

74HC161

74HC107

LOAD

4.11

9.12

1,8

CLK 1,2

CLR1

CLR2

CLR1

CLK2

CLK1

CLR2

K1,K2

J1,J2

K1,K2

11 10 13

1.8

4.11

CLK SI

D5V

LRSEL

4/8 fsel

DGND

A5V

AGND

RREF

LREF

LOUT

LRCLK

ROUT

7,8

0.1u

5,12

47u

•

U1 = 74HC04
U2 = 74HC161
U3 = 74HC161
U4 = 74HC107
U5 = 74HC107
U6 = 74HC08
U7 = 1458
U8 = NEC uPD6376
U9 = 1458

0.1u

22u

0.1u

22u

0.1u

+12V

-12V

U1, U4

U5, U6

P2-7

P2-8

1070F2-8 EP Circuit

Figure 2-8. Eye Pattern Circuit

Summary of Contents for RFX144V24-S23

Page 1: ...RFX144V24 S23 and RFX96V24 S23 MONOFAX Modems Designer s Guide Preliminary Order No 1070 February 14 1996...

Page 2: ...ents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent rights of Rockwell International other than for circuitry embodie...

Page 3: ...MEMORY ACCESS TO DSP RAM 4 1 4 1 1 Host Programmable Data 4 1 4 1 2 Host DSP RAM Read and Write Procedures 4 1 4 1 3 DSP RAM Read Procedure 4 1 4 1 4 DSP RAM Write Procedure 4 2 4 2 DIAGNOSTIC DATA SC...

Page 4: ...harts 9 8 9 2 ERROR CORRECTION MODE 9 25 9 2 1 General 9 25 9 2 2 ECM Frame Structure 9 25 9 3 SIGNAL RECOGNITION ALGORITHM 9 29 9 3 1 FSK vs High Speed 9 29 9 3 2 FAX vs Voice 9 29 9 4 SHORT TRAIN EX...

Page 5: ...RFORMANCE 13 1 13 1 TYPICAL BIT ERROR RATES 13 1 13 2 TYPICAL PHASE JITTER 13 1 13 3 DTMF PERFORMANCE 13 1 14 MODEM INTERFACE CIRCUIT 14 1 14 1 CIRCUIT AND COMPONENTS 14 1 14 1 1 Crystal Oscillator Sp...

Page 6: ...6 Alpha zero Center Frequency 6 6 Figure 7 1 Autodialer Flowchart 7 5 Figure 8 1 Encoder Implementation 8 2 Figure 8 2 AGC Operation 8 4 Figure 8 3 AGC Implementation 8 5 Figure 8 4 AGC Implementation...

Page 7: ...Figure 11 2 High Speed and V 21 Transmit Signal Path 11 3 Figure 11 3 PDE Block Diagram 11 3 Figure 11 4 PDE Response 11 4 Figure 11 5 Digital Cable Equalizer Frequency Response 11 5 Figure 11 6 Recei...

Page 8: ...peed Status Bit Timing 3 26 Table 3 3 Power On Reset Self Test Values 3 29 Table 4 1 Modem DSP RAM Access Codes 4 3 Table 4 2 Modem DSP RAM Access Codes SBRAM 4 4 Table 5 1 Transmitter and Receiver In...

Page 9: ...es of stored voice messages in 4 Mbits of memory This voice codec allows the host controller to efficiently store and playback digital incoming messages ICMs and outgoing messages OGMs The ADPCM audio...

Page 10: ...IA 28 Pin PLCC Maximum Line Speed DigiTalk Voice and ADPCM Audio Codecs V24 Full Duplex Speakerphone S Full Duplex V 23 23 RFX144V24 S23 14 4 kbps RFX144V24 S 14 4 kbps RFX144V24 23 14 4 kbps RFX144V2...

Page 11: ...M usage DTMF detect tone detect and tone transmit Pitch synchronized fast and slow playback Near end echo cancellation ADPCM audio codec V24 Option High fidelity recording and playback of audio signal...

Page 12: ...ogrammable dual tone generation Programmable tone detection Programmable interface memory interrupt Programmable ring detector Eight general purpose input GPI and eight general purpose output GPO pins...

Page 13: ...hs The modem includes an optional host programmable Receive Compromise Equalizer for V 23 1200 bps reception and Caller ID mode 23 Option Transmitted Data Spectrum The transmitted data spectrum is sha...

Page 14: ...nal path thus enabling tone detection to be independent of the receiver status The tone detectors operate in all modes except V 23 without tone detectors and speakerphone where only tone detector one...

Page 15: ...ms 1152 ms V 27 ter 2400 bps Short Train 69 ms 276 ms V 21 Channel 2 300 bps 14 ms 14 ms Table 1 4 Turn Off Sequence Times Configuration Data and Scrambled Ones No Trans mitted Energy Total V 17 Long...

Page 16: ...ansmit and receive are supported Room Monitor Mode Room Monitor Mode allows the remote end user to monitor the local room activity by listening to audio captured by the microphone connected to the XIA...

Page 17: ...d with a small circle the input activates on a falling edge If no circle is shown the input activates on a rising edge The MDP pin assignments are shown in Figure 2 2 and hardware interface signals ar...

Page 18: ...NC EYECLK X Y 1070F2 1 IF Signals IRQ1 5V CRYSTAL XTLI XTLO RXD TXD DCLK RTS CTS RLSD 5V IRQ2 OH TALK RINGD RIN TXA1 TXA2 SPKR ANALOG SWITCH MIC SPEAKER SPEAKER MICROPHONE CIRCUIT TELEPHONE LINE TELEP...

Page 19: ...GPI5 GPI4 GPI3 GPI2 READ CS NC RS4 RS3 RS2 RS1 RS0 VDD1 D7 D6 D5 D4 D3 D2 D1 D0 WRITE DGND1 RXOUT RMODE TSTROBE TRESET DGNDA1 NC TMODE TXDAT AVDD TALK AGND1 TXA1 TXA2 DGNDA2 RXD TXD GPI1 DGND5 RTS GP...

Page 20: ...MI MDP RMODE 18 73 XTLI I Crystal Clock Circuit 24 TXDAT MI MDP SR4OUT 90 74 XTLO O Crystal Clock Circuit 25 AVDD PWR VCC through power decoupling filter 75 XCLK OD Diagnostic Circuit 26 TALK OD Line...

Page 21: ...DP IACLK 50 18 TXA2 SPKLO O DD Analog Switch Line Interface SPKLO 5 NC NC 19 NC NC 6 RXDAT MI MDP SR4IN 82 20 P5VT PWR To P5VD 14 P5VR 28 to VCC through a power decoupling filter 7 RMODE MI MDP RMODE...

Page 22: ...e modem configuration read or write channel and diagnostic data and supervise modem operation by writing control bits and reading status bits Note that the modem should not be continuously selected fo...

Page 23: ...ion must be delayed by at least 2 YCLK cycles IRQ1 IRQ2 OC OC Interrupt Request IRQ1 and IRQ2 interrupt request outputs may be connected to the host processor interrupt request input in order to inter...

Page 24: ...on response time is 816 baud times for V 17 V 33 V 29 and V 27 ter long train 492 baud times for V 17 V 33 and 486 baud times for V 27 ter short train The RLSD on to off time is 40 5 ms for V 17 V 33...

Page 25: ...case TALK active opens the relay to disconnect the handset from the telephone line SPEAKER INTERFACE SPKR O DF Received Analog Output The SPKR output reflects the received analog input signal The SPKR...

Page 26: ...EXY on the falling edge of EYECLK EYESYNC OA Serial Eye Pattern Strobe EYESYNC is a strobe that indicates whether the EYEX or EYEY portion of EYEXY is being shifted The EYESYNC frequency is equal to t...

Page 27: ...is a single ended microphone Input from the analog switch circuit The input impedance is 70k ohms REFERENCE SIGNALS AND MODEM INTERCONNECT POR MI Power On Reset Connect to MDP POR 47 SLEEP MI Sleep Co...

Page 28: ...V Type IB and IC 400 Input Leakage Current I IN 2 5 ADC VIN 0 to 5V VCC 5 25V Types IA and ID Output High Voltage V OH VDC Type OA and OB 3 5 V CC ILOAD 100 A Type OD ILOAD 0 mA Output Low Voltage V O...

Page 29: ...7 VP P 8000 Hz sample rate Reference Voltage 2 5 VDC DC Offset Voltage 200 mV SPKR O DF Minimum Load 300 Maximum Capacitive Load 0 01 F Output Impedance 10 Maximum AC Output Voltage 2 0 VP P Reference...

Page 30: ...C for maximum values 3 Input Ripple less than 0 1 Vpeak peak 4 Data based on 49 92 MHz crystal frequency Table 2 8 Absolute Maximum Ratings Parameter Symbol Limits Units Supply Voltage V DD 0 5 to 7 0...

Page 31: ...READ WRITE a 8085 Bus Compatible EN85 L TDHW TWDS 1070F2 4 MP WF b 6500 Bus Compatible EN85 H TP2CH TDHR TDA TRS TCS THC TRS TCS THC TDA TDHR TRS TCS THC TRS TCS THC TWDS TDHW D0 D7 02 R W R0 RS4 CS...

Page 32: ...k High TP2CH 70 ns Notes 1 CS and READ must not both be active continuously 2 A read or write operation following a write operation must be delayed by at least 2 YCLK cycles 3 A read or write operatio...

Page 33: ...S23 Modem Designer s Guide 1070 2 17 LRCLK LSB LSB MSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1070F2 7 EP Timing EYESYNC EYECLK EYEXY EYECLK Fig...

Page 34: ...13 13 9 12 10 10 5 1 8 CLK 1 2 CLR1 CLR2 CLR1 CLK2 CLK1 CLR2 K1 K2 J1 J2 J1 J2 K1 K2 Q1 Q2 9 12 10 9 15 9 16 15 5 4 6 11 10 13 6 11 5 6 U6 1 2 1 8 4 11 5 2 Q2 Q1 CLK SI D5V LRSEL 4 8 fsel DGND A5V AGN...

Page 35: ...rameter values from DSP RAM is described in Section 4 3 1 1 Interface Memory Map A memory map of the 32 addressable registers in the modem is shown in Figure 3 1 These 8 bit registers may be read or w...

Page 36: ...A BUFFER DBUFF Speakerphone 0F TONEIE TONEXE AGCIE AGCXE ECHOAT 0011 00 Voice Audio Codec Control 0E TTONEE VOLUP VOLDWN SP HS MUTEI MUTEX MICLVL 0010101 High Speed Status 0F FED CTSP CDET XXXX 0E FSK...

Page 37: ...00 RAM Address 2 ADD2 in conjunction with AREX2 contains the RAM address used to access the modem s X and Y Data RAM CR2 0 or X and Y Coefficient RAM CR2 1 via the X RAM Data 2 LSB and MSB words 12 0...

Page 38: ...he modem When B1I1E is a 0 B1A has no effect on IRQ1 and B1IA See B1A and B1IA B1I2E 1E 1 0 Buffer 1 Interrupt 2 Enable When control bit B1I2E is a 1 IRQ2 is enabled for Buffer 1 i e the modem will as...

Page 39: ...sequence continuous Space V 23 BRKS 14 6 0 Break Send Parallel Mode When control bit BRKS is set in parallel mode the modem will send continuous Space When BRKS is reset the modem will transmit paral...

Page 40: ...ive tone detect and DTMF 24 V 23 23 Option 22 V 23 receive 1200 bps Caller ID tone detect 80 RTS on Dual single tone transmit RTS off Tone detectors 82 RTS on 8 bit Audio Mode transmit DTMF detect and...

Page 41: ...Monitor Voice coder and decoder with optional error correction coding CDEN DCDEN HDLC DTMF detect and three tone detectors with a local echo canceller during decoder operation Dual single tone transm...

Page 42: ...st can enable the assertion of IRQx upon the setting of B2A Bit 0 of DBUFF is the first bit of the 8 bit input or output In the V 23 configuration CONF 24 in parallel data mode PDM bit 1 the host obta...

Page 43: ...modem sets status bit DTMFD to a 1 when a DTMF signal has been detected that satisfies all specified DTMF detect criteria The host must reset this bit after reading the DTMF Output Word 1C 0 7 otherwi...

Page 44: ...he beginning of training See status bit P1 The setting of the EPT bit must be followed by the setting of the SETUP bit to become active EQFZ 09 5 0 Equalizer Freeze When control bit EQFZ is a 1 updati...

Page 45: ...SK flags have been detected in a high speed receiver mode FSK7E is valid after bit FSKFLS transitions from 1 to 0 FSK7E is not valid in V 27 ter short train modes FSKFLS 0E 7 0 FSK FLAG 7E Search When...

Page 46: ...bits in the register specified by ITADRS according to the ANDOR bit and the TRIG bits if PIE is set by the host and PIREQ is reset by the host MICLVL 0E 0 1 01 Microphone Volume Level In speakerphone...

Page 47: ...When configured as a receiver the modem sets the OVRUN bit to a 1 if a receive overrun condition occurs To detect the next overrun condition the host must reset this bit P1 0C 1 P1 Sequence When the m...

Page 48: ...R bit is valid in all modes except tone voice audio codec audio and speakerphone PIE 1F 4 0 Programmable Interrupt Enable When control bit PIE is enabled PIE is a 1 and the interrupt condition is true...

Page 49: ...e IIA Line output The setting of the RMM bit must be followed by the setting of the SETUP bit to become active RTSP 07 7 0 Request To Send Parallel The one state of control bit RTSP begins a transmit...

Page 50: ...1 microphone speaker operation is enabled when SP HS is a 0 handset in place of microphone speaker is assumed for handset operation SQEXT 07 2 0 Squelch Extend Control bit SQEXT determines the length...

Page 51: ...pon the number of stop bits and word size selected V 23 The modem will reset UE whenever it sets TDBE V23HDX 15 0 0 V 23 Half Duplex When control bit V23HDX is set the modem operates in V 23 1200 half...

Page 52: ...rnal RAM from the locations addressed by AREX2 ADD2 and CR2 and stores the data into the X RAM Data 2 registers and Y RAM Data 2 registers respectively XDAL1 02 0 7 X RAM Data 1 LSB XDAL1 is the LSB o...

Page 53: ...nificant bit of register DBUFF last The flowchart shown in Figure 3 2 may be used for parallel data transfer 3 2 2 Programmable Interrupt Feature The interface memory interrupt feature enables the hos...

Page 54: ...F 10 7 0 1 PDM 07 5 1 SETUP 1F 0 SETUP 1F 0 0 1070F3 2 END B2A 1E 3 1 CTSP 0F 1 1 1 RTSP 07 7 END No Yes Yes Yes Yes CONTINUE CONTINUE No No No No No Yes Yes READ DBUFF B2A 1E 3 1 WRITE DBUFF 0 RTSP 0...

Page 55: ...s All tone detectors are functional in this mode 16 Bit Audio Mode Transmitter This mode allows the transmission of high quality 16 bit audio messages 16 bit Audio Mode transmitter operates when CONF...

Page 56: ...rd 1C 0 3 If DTDET is not set to a 1 then the received signal has failed one or more criteria and consequently the modem resets EDET and resumes its search After the on time criteria is satisfied the...

Page 57: ...the modem enters the idle mode the modem will reset FSKFLS and FSK7E bits to a 0 If FED is on then the modem will set FSKFLS to a 1 and start the detection process After the completion of the detectio...

Page 58: ...In parallel mode PDM 1 start stop data length and parity selection is done via the modem interface memory During transmission the host need only provide data bits to the TBUFFER register and the modem...

Page 59: ...23HDX 1 ANS 0 for Tx Rx 1200 Parallel Data Mode Desired Set PDM 1 Select Data Bits 5 6 7 8 Select Stop Bits 1 2 Select Parity Mark Space Even Odd Set PDM 0 Full Duplex Selected Set SETUP Bit RTSP 0 Cl...

Page 60: ...26 7 20 0 6 3 4 2 10 9 13 20 40 ms V 33 V 17 Short 187 5 20 0 106 7 15 8 0 20 0 4 6 4 2 10 9 13 20 40 ms V 29 Long 187 5 20 0 53 3 160 0 20 0 6 3 4 2 4 2 5 20 34 ms V 29 Short 187 5 20 0 41 7 25 8 0...

Page 61: ...de 1070 3 27 Analog Signal P1 P2 PR PR RXD PNSUC PNSUC P2 PNDET PN PR SCR1 SCR1 DATA CTSP DATA CDET SIDLE SIDLE P1 P2 PN PR SCR1 DATA T1 T2 T3 T4 T5 T6 TRANSMIT RECEIVE T7 T7 T8 T8 T8 T9 1070F3 7a HS...

Page 62: ...Guide 3 28 1070 min T12 T10 T11 Data 8 bits SCR1 T13 Analog Signal RTSP P1 SIDLE SIDLE PNDET PNDET P2 P2 PN PN PR PR PNSUC SCR1 SCR1 RXD DATA CTSP DATA CDET 1070F3 7b HS Timing See Table 3 2 Note Figu...

Page 63: ...gisters for about 4 ms or until register 10 is read by the host Table 3 3 Power On Reset Self Test Values Contents Register Hex Value Hex Multiplier checksum upper word 19 46 Multiplier checksum lower...

Page 64: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 3 30 1070 This page is intentionally blank...

Page 65: ...ring to RAM Access 1 and RAM Access 2 respectively To access the main RAM write the desired RAM access code into ADDx and AREXx x 1 2 Bits 0 through 6 and AREXx x 1 2 of the access code specify the RA...

Page 66: ...t WRT1 and or WRT2 to a 1 to inform the DSP that a RAM write will occur when ACC1 and or ACC2 is set to a 1 4 Write the desired data into the interface memory RAM Data registers YDAL1 and YDAM1 and or...

Page 67: ...Turn off Threshold 0 0 1 0 0 B7 0 1 21 Receiver Sensitivity MAXG 0 0 1 0 0 24 2 3 29 Minimum On Time DTMF 0 0 1 0 0 1F 2 3 30 Minimum Off Time DTMF 0 0 0 0 0 1F 2 3 31 Minimum Cycle Time DTMF 0 0 0 0...

Page 68: ...0 0 1 0 1C 0 1 70 Speakerphone Transmit Speech Active 0 0 0 1 0 1E 0 7 71 Speakerphone Receive Speech Active 0 0 0 1 0 1E 0 6 Notes 1 Parameter numbers refer to corresponding numbers in Section 4 2 Fo...

Page 69: ...ore to read End Read Yes Notes 1 If RAM Access 1 is used x 1 If RAM Access 2 is used x 2 Either RAM Access 1 or 2 may be used to read or write RAM 2 RAM access 2 is not available in Voice Audio Codec...

Page 70: ...Sample Word Format 8 bits signed twos complement Equation VINT Volts A D Sample Word 8 x 0 85 128 2 5V VEXT VINT LOG10 1 AGC Gain dB 20 Where VEXT is the input to the IA VINT is the output of the IA a...

Page 71: ...termination Ps output power in dBm with a series 600 ohm resistor into a 600 ohm load Ps Po 6 Convert Transmit Output Level to hexadecimal and store in RAM Default Value 7FFFh Note For the modem inte...

Page 72: ...ary BOUNDARY BOUNDARY y x 0 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 P1 P2 P1 x1 iy1 P2 x2 iy2 P2 P1 x2 x1 i y2 y1 REAL ERROR IMAGINARY ERROR 1070F4 1a i R Error Vector Maximum Values Configura...

Page 73: ...Threshold No 21 Receiver Sensitivity MAXG Three parameters can be programmed by the host to control the RLSD turn on and turn off thresholds 1 Post AGC Turn on Threshold 2 Post AGC Turn off Threshold...

Page 74: ...maximum period of the DTMF signal beginning when the signal energy drops below the turn off threshold and ending when the signal energy returns that is considered to be part of the on time The defaul...

Page 75: ...se h Range 0 to 7FFFh Default Value 2800h CONF 21h 0C2Eh CONF 90h 92h 94h or 98h No 37 Positive Twist DTMF This parameter controls the acceptable positive twist for the DTMF signals Decreasing this pa...

Page 76: ...the tone detector This parameter is used for all 3 filters Format 16 bits twos complement positive value Equation 215 1 Threshold desired h Default Value 7000h No 48 Maximum Samples per Ring Frequency...

Page 77: ...Bits Caller ID only This parameter selects the number of bits per character for Caller ID mode including one start bit and one stop bit Caller ID mode does not use a parity bit Characters from 5 to 8...

Page 78: ...Audio Energy AGC Slew Rate Slew rate for the Energy AGC The slew rate controls how rapidly the AGC will adapt the average message energy to the AGC reference level Larger smaller slew rate values corr...

Page 79: ...ult value is loaded each time the modem is configured to Voice Codec Mode CONF 90h or 98h or Audio Codec Mode CONF 92h or 94h Format 16 bits signed twos complement Equation Level 256 x 757 Where x AGC...

Page 80: ...an 8 ohm or 50 ohm speaker coil directly It is recommended that the SPKR output be connected to an external audio power amplifier input No 70 Speakerphone Transmit Speech Active The speakerphone tran...

Page 81: ...Range 040Ch 16C3h 30 dB to 15 dB referenced to maximum digital signal 7FFFh Default Value 16C3h 15 dB No 74 Speakerphone Transmit AGC Slew Rate The AGC slew rate determines how rapidly the AGC algori...

Page 82: ...r will be gradually decremented to 0 The default value is loaded each time the modem is configured to Speakerphone Mode CONF 91h Format 16 bits positive two s complement Equation Hangover 8 x Where x...

Page 83: ...he following frame If separate ending and beginning flags are used the final zero in the ending flag of one frame may also serve as the first zero of the beginning flag in the following frame This pro...

Page 84: ...rated shorthand representation of the received sequence If any difference occurs the received frame was in error and should be re transmitted The FCS computation is done on all fields within the frame...

Page 85: ...the receiver s FCS register The shift register will contain 1111000010111000 if the frame has been received correctly 4 The ending flag is transmitted The signal timing is illustrated in Figure 5 4 F...

Page 86: ...ags by either waiting to load data into DBUFF or by doing a diagnostics write to RAM see Flag Transmition and Reception Section The host can then load the first byte when RX goes low for the first fra...

Page 87: ...Reception Rate The HDLC as implemented in the modem runs under the following transmitter and receiver modes V 33 and V 17 V 29 V 27 ter V 21 V 21 with DTMF receiver 5 2 3 Transmitter and Receiver Init...

Page 88: ...M1 and write 02h into YDAL1 Another method exists for sending extra flags The host must simply do nothing since flags are transmitted as the default condition In other words after the final zero in a...

Page 89: ...t byte of data of the next frame To terminate data transmission the host may turn off RTS or RTSP when the modem sets EOF to a 1 The modem will then automatically transmit the 16 bit FCS and at least...

Page 90: ...g off RTS input or by resetting the RTSP bit in the interface memory In both cases the following events will occur 1 When AEOF is set to a 0 and if exiting after making sure the modem took the data in...

Page 91: ...emory 5 Wait for an interrupt If it is caused by B2A being set read the data in DBUFF This indicates that the first byte of the first frame is ready for host reading If the interrupt is caused by EOF...

Page 92: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 5 10 1070 This page is intentionally blank...

Page 93: ...ts interface memory bits FR1 FR2 and FR3 to a 1 when tone detectors 1 2 and 3 detect energy above their respective threshold This application note presents a method of tuning these detectors to any fr...

Page 94: ...P 1 1 1 2 2 2 and P 2 1 1 2 2 2 Upon power up these poles lie on a circle of radius 0 994030884 on the Z plane The radius of the tone detector circle was chosen so that each filter has a high Q withou...

Page 95: ...ersus center frequency O as shown in Figure 6 6 Three equations corresponding to three linear approximations result 0 0 104 319 O 78 62 32767 400 O 1100 Hz Eq 12a 0 0 44 275 O 104 32767 1100 O 1650 Hz...

Page 96: ...23 Modem Designer s Guide 6 4 1070 GAIN dB FREQUENCY Hz 1070F6 2 500 1000 2000 3000 3500 Figure 6 2 Typical Single Filter Response GAIN dB FREQUENCY Hz 1070F6 3 500 1000 2000 3000 3500 Figure 6 3 Typi...

Page 97: ...s Guide 1070 6 5 UNIT CIRCLE r 1 Im Z 90 Fs 4 Hz j1 CONJUGATE POLE PAIR 1 360 Fs Hz Re Z DOUBLE ZERO 180 1 Fs 2 Hz j1 270 3Fs 4 Hz TONE DETECTOR CIRCLE r 0 994030884 r 0 994030884 2 1 2 2 2 1 2 2 1 1...

Page 98: ...SPONSE COMPACTOR THRESHHOLD FREQUENCY Hz GAIN dB O B O A O O A O B 2 2 1070F6 5 Figure 6 5 Bandwidth and Offset Frequencies 500 1000 3000 2500 2000 1500 EQ 12a EQ 12b EQ 12c 0dB CURVE FREQUENCY Hz ALP...

Page 99: ...gured to Voice or Audio Codec modes that use either 4000 or 8000 Hz sample rates and when configured for Audio mode using the 8000 Hz sample rate For a tone detector response time of 0 1 seconds 0 1 s...

Page 100: ...2 2 C0C4 0 49401855 1850 Hz 24 Hz A 18 Hz 0 0 0180 0 01171875 1 1 2 2 0000 0 00000000 1 2E37 0 36105347 1 2B69 0 33914184 2 2 C0C4 0 49401855 1650 Hz 23 Hz A 18 Hz 0 0 0170 0 01123047 1 1 2 2 0000 0...

Page 101: ...49403363 1850 Hz 30 Hz A 18 Hz 0 0 0181 0 01174963 1 1 2 2 0000 0 00000000 1 10BD 0 13077181 1 0D2A 0 10284738 2 2 C0C5 0 49403363 1650 Hz 23 Hz 0 0 0113 0 00839260 1 1 FE7B 0 01187170 2 2 0113 0 0083...

Page 102: ...460815 1 0000 0 00000000 2 FF69 0 00460815 0 01D0 0 01416016 1 0000 0 00000000 2 FE30 0 01416016 1 97A8 0 81518555 2 C12D 0 49081421 1 9588 0 83178711 2 C120 0 49121094 0145 0 00991821 7EBB 0 99008179...

Page 103: ...be less than 8 dBm When connecting the modem circuit to the PSTN by means of a data access arrangement DAA set for permissive mode the DAA gain is 9 dB The modem circuit must therefore drive the DAA i...

Page 104: ...DIAL or REDIAL When entering at AUTO DIAL the host prompts the user to enter a phone number which is then stored in the phone number buffer When entering at REDIAL the routine dials the number previo...

Page 105: ...0 0 22 0 0 0 65AB 0 23 0 0 0 7FFF 3 0 21 1 0 0 1296 0 22 1 0 0 2763 0 22 0 0 0 65AB 0 23 0 0 0 7FFF 4 0 21 1 0 0 1488 0 22 1 0 0 203D 0 22 0 0 0 65AB 0 23 0 0 0 7FFF 5 0 21 1 0 0 1488 0 22 1 0 0 23A0...

Page 106: ...1 0 0 1918 0 22 1 0 0 2B8C 0 22 0 0 0 65AB 0 23 0 0 0 7FFF 7 5 SINGLE TONE GENERATION In OEM equipment that combines the features of a modem with those of a telephone handset the tone generators may b...

Page 107: ...and disable interrupts Set DAA to off hook Start 3 second timer Request coupler cut through from DAA Print DIALING AUTODIAL REDIAL Save current configuration and select DTMF transmit configuration Cou...

Page 108: ...g RAM write routine of Figure 4 2 Delay for 95 ms 1 RTSP 07 7 Select one set of four coefficents from Table 7 2 based on value of BYTE Read next BYTE from number buffer 2Fh BYTE 3Ah Delay for 70 ms 0...

Page 109: ...Restore interrupt status Restore modem configuration Start 3 second timer FR1 08 5 1 Y Time out Print NO ANSWER and set DAA to on hook N Y ANS DET N Print WAITING FOR ANSWER Select FSK Configuration...

Page 110: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 7 8 1070 This page is intentionally blank...

Page 111: ...le during room monitor operation 8 1 VOICE ENCODER AND AUDIO ENCODER Encoder error correction coding must be enabled for voice encoder compression of messages with error correction and disabled for me...

Page 112: ...1A 3 DCVOX 14 5 ENUPDT 14 5 AGCSEL 14 6 TND8K 14 7 HDLC 07 0 READ DBUFF 10 0 7 TO RESET B2A 1E 3 ENABLE ENCODER CDEN 1A 4 1 RTSP 07 6 0 RTSP 07 06 1 TONE TRANSMIT No Yes VOVUN 17 3 1 READ ENCODER OUTP...

Page 113: ...alues must be adjusted to establish the preferred playback level if different from the default selection Selected parameter values are to be written to modem RAM using RAM Access see Section 4 after e...

Page 114: ...APTATION THRESHOLD No G G E Eref SR see note No DCVOX 14 5 1 VOX 17 3 1 No No Note G AGC Gain E RMS Energy Eref AGC Energy Reference Level SR AGC Slew Rate RMS ENERGY AGC ADAPTATION THRESHOLD Yes Yes...

Page 115: ...ACK MESSAGE PLAYBACK LEVEL GREATER THAN REFERENCE PLAYBACK LEVEL PLAYBACK LEVEL LESS THAN REFERENCE PLAYBACK LEVEL END No No DECREASE AGC ENERGY REFERENCE LEVEL DECREASE GAIN ADAPTATION THRESHOLD INCR...

Page 116: ...SSAGE PLAYBACK LEVEL LESS THAN REFERENCE PLAYBACK LEVEL END Yes DECREASE AGC MAXIMUM GAIN RESTORE MAXIMUM GAIN TO PRIOR MAXIMUM GAIN No AGC SLEW RATE SLEW RATE 7FFFh ENCODE A MESSAGE WITH UNIFORM ENER...

Page 117: ...70 8 7 Maximum Gain Output dB Energy Reference Level Gain Adaptation Threshold Input dB Gain Adaptation Threshold Energy Reference Level Maximum Gain Energy Reference Level Energy Reference Level 25 d...

Page 118: ...rence Level Repeat until playback levels are equal Note that if the message playback level remains distinctively greater than the reference message playback level although the Energy Reference Level h...

Page 119: ...o decoder s input is a fixed length data block of 120 bytes at 32 kbps or 90 bytes at 24 kbps A data underrun condition will occur when the decoder has completed decoding and playback of its last data...

Page 120: ...07 0 READ DBUFF 10 0 7 TO RESET B2A 1E 3 ENABLE DECODER DCDEN 1A 5 1 DECODER PAUSE OR END PLAYBACK No Yes VOVUN 17 3 1 WRITE DECODER INPUT DBUFF 10 0 7 B2A 1E 3 1 No Yes Yes DTMF AND TONE DETECTION N...

Page 121: ...y proceed as follows 1 The remote end user is greeted by an outgoing message OGM from the voice or audio decoder The remote end user sends a known DTMF sequence requesting Room Monitor that is receive...

Page 122: ...r filters need to be designed with the 8000 Hz or 4000 Hz sample rate see Section 6 The 4000 Hz sample rate is required only when the voice encoder is enabled during Room Monitor operation When using...

Page 123: ...tones In this case the modem looks for the preamble of flags see phase B 9 1 2 Phase B The pre message procedure consists of the handshake One machine sends an identification signal and the other mach...

Page 124: ...K HDLC FORMAT TRAINING CHECK HIGH SPEED TRAIN FOLLOWED BY 1 5S OF ZEROS CONFIRMATION TO RECEIVE 300 BPS FSK HDLC FORMAT CALLING TONE 1100 Hz 0 5S ON 3S OFF CALLING TONE INDICATE NON SPEECH TERMINAL CA...

Page 125: ...DDRESS AREX1 SET CR1 AND RESET BR1 DR1 21h ADD1 0 AREX1 1 CR1 0 BR1 0 DR1 LOAD PARAMETERS FOR FREQUENCY 1Dh YDAM1 1 0 7 55h YDAL1 0 0 7 ENABLE DIAGNOSTICS 1 1 ACC1 ENABLE DIAGNOSTICS 1 1 ACC1 B1A 1E 0...

Page 126: ...E FOR FSK 20h CONF 6 0 7 1 SETUP 1F 0 NO NO NO NO NO SETUP 0 MONITOR FR2 BIT FR2 8 6 1 YES YES YES YES TIME OUT 3 SECONDS DELAY 600ms CHECK FR2 BIT FR2 0 CHECK FR2 BIT FR2 1 DELAY 3 6 SECONDS CNG DETE...

Page 127: ...AREX1 0 CR1 0 BR1 0 DRI DISABLE DIAGNOSTICS 1 0 ACC1 5 7 DISABLE DIAGNOSTICS 1 0 ACC1 ENABLE DIAGNOSTICS 1 1 ACC1 ENABLE DIAGNOSTICS 1 1 ACC1 LOAD PARAMETERS FOR FREQUENCY 38h YDAM1 1 0 7 00h YDAL1 0...

Page 128: ...9 6 1070 START CED NOT DETECTED CED DETECTED CONFIGURE FOR FSK 20h CONF 6 0 7 1 SETUP 1F 0 NO NO SETUP 0 TIME OUT DELAY 2 6 SECONDS CHECK FR1 BIT FR1 1 YES YES NO YES NO YES PHASE A 1070F9 6 MONITOR F...

Page 129: ...onds 10 Since the called unit knows it will be receiving 1 5 seconds of zeros the host can make a decision whether the line is good enough at the chosen data rate or fallback to a slower speed After c...

Page 130: ...ty of requesting operator intervention If operator intervention is required further facsimile procedures commence at the beginning of phase B The called station might respond to an EOM MPS or EOP sign...

Page 131: ...executed and the End of Frame bit is checked to see if it is the end of the frame The Cyclic Redundancy Check CRC bit is looked at to determine if the current frame was received correctly Figure 9 16...

Page 132: ...TURN TO CONTROL RTC INDICATING END OF DOCUMENT TRANSMISSION FORMAT SIX CONSECUTIVE EOLS DATA EOL DATA EOL DATA FILL EOL START OF PHASE C T T T DATA EOL END OF PHASE C RTC EOL EOL EOL EOL EOL EOL T MIN...

Page 133: ...em Designer s Guide 1070 9 11 START END LOW SPEED CONFIGURATION TX PREAMBLE ENABLE BUFFER 2 INTERRUPT 1 1 B2I1E 1E 5 INITIALIZE BYTE COUNT IRQ TX ROUTINE RESET RTSP 0 RTSP 7 7 EOF 0 NO YES 1070F9 9 Fi...

Page 134: ...MABLE INTERRUPT SET UP ENABLE PROGRAMMABLE INTERRUPT 1 PIE 1F 4 1 PIDR 5 5 LOAD REGISTER ADDRESS 14h ITADRS A 0 4 SPECIFY BITS TO BE MASKED 0Ch ITBMSK B 0 7 RESET ANDOR BIT 0 ANDOR A 5 SET FOR DC TRIG...

Page 135: ...3 LOW SPEED CONFIGURATION RTI CONFIGURE FOR V 21 FSK 20h CONF 06 0 7 SETUP FOR PARALLEL DATA MODE 1 PDM 7 5 ENABLE HDLC MODE 1 HDLC 7 0 0 AEOF 15 5 1 SETUP 1F 0 PROGRAMMABLE INTERRUPT SETUP SETUP 0 NO...

Page 136: ...23 and RFX96V24 S23 Modem Designer s Guide 9 14 1070 RTI TRANSMIT PREAMBLE SET RTSP 1 RTSP 7 7 LOAD 7Eh INTO DBUFF REGISTER DELAY 1 SECOND WAIT FOR CTSP CTSP F 1 1 NO YES 1070F9 12 Figure 9 12 Transmi...

Page 137: ...TI NO NO WAIT FOR INTERRUPT IRQ1 0 ERROR INTERRUPT NOT CAUSED BY MODEM LOAD DATA INTO BUFFER 2 SET END OF FRAME BIT 1 EOF 9 2 DECREMENT BYTE COUNT YES NO YES 1070F9 13 POLL BUFFER 2 AVAILABLE B2A 1E 3...

Page 138: ...E 1E 5 IRQ LOW SPEED RX ROUTINE CHECK IF FRAME IS IN ERROR CRC 9 1 1 RESET EOF BIT 0 EOF 9 2 RESET EOF BIT 0 EOF 9 2 RESET PROGRAMMABLE INTERRUPT REQUEST BIT 0 PIREQ 1F 3 RESET PROGRAMMABLE INTERRUPT...

Page 139: ...RUPT REQUEST BIT 0 PIREQ 1F 3 ABORT IDLE SEQUENCE IS BEING RECEIVED RTI ERROR INTERRUPT NOT CAUSED BY MODEM WAIT FOR INTERRUPT IRQ1 0 POLL BUFFER 2 AVAILABLE BIT B2A 1E 3 1 POLL PROGRAMMABLE INTERRUPT...

Page 140: ...gner s Guide 9 18 1070 HIGH SPEED CONFIGURATION DISABLE HDLC MODE 0 HDLC 7 0 1 SETUP 1F 0 SETUP 0 CONFIGURE FOR HIGH SPEED CONF CODE FROM TABLE 3 1 CONF 6 0 7 14400 TO 2400 BPS RTI NO YES 1070F9 16 Fi...

Page 141: ...Modem Designer s Guide 1070 9 19 SETUP RTSP 1 RTSP 7 7 PRELOAD 00 INTO DBUFF RESET RTSP 0 RTSP DELAY 1 5 SECONDS WAIT FOR CTSP TO BE SET CTSP F 1 1 END NO YES START HIGH SPEED CONFIGURATION 1070F9 17...

Page 142: ...RTSP 1 RTSP 7 7 PRELOAD DBUFF WITH DUMMY DATA WAIT FOR CTSP TO BE SET CTSP F 1 1 HIGH SPEED CONFIGURATION ENABLE BUFFER 2 INTERRUPT 1 1 B2I1E 1E 5 INITIALIZE BYTE COUNT HIGH SPEED IRQ TX ROUTINE RESET...

Page 143: ...1E 3 1 LOAD COMPRESSED T 4 DATA INTO DBUFF ERROR INTERRUPT NOT CAUSED BY MODEM DECREMENT BYTE COUNT RTI NO NO NO YES YES YES HIGH SPEED IRQ TX ROUTINE WAIT FOR INTERRUPT IRQ1 0 MORE TO TRANSMIT BYTE...

Page 144: ...Modem Designer s Guide 9 22 1070 START HIGH SPEED CONFIGURATION ENSURE VALID TRAIN PERFORM DUMMY READ OF DBUFF ENABLE BUFFER 2 INTERRUPT 1 1 B2I1E 1E 5 IRQ HIGH SPEED RX ROUTINE END 1070F9 20 Figure 9...

Page 145: ...S23 Modem Designer s Guide 1070 9 23 B2A 1E 3 1 READ DATA IN DBUFF REGISTER RTI NO NO NO YES YES YES HIGH SPEED IRQ RX ROUTINE WAIT FOR INTERRUPT IRQ1 0 MORE TO RECEIVE 1070F9 21 Figure 9 21 High Spee...

Page 146: ...odem Designer s Guide 9 24 1070 ENSURE VALID TRAIN RTI WAIT FOR SILENCE IDLE BIT TO BE SET SIDLE C 0 1 WAIT FOR PNSUC 08 3 1 VALID TRAIN TIMEOUT INVALID TRAIN NO NO NO YES YES YES 1070F9 22 Figure 9 2...

Page 147: ...Control Field for the Facsimile Coded Data block FCD is 60 The frame number follows the FCF for FCD followed by the facsimile data Pad bits such as EOL Tag and Align bits follow the facsimile data Fi...

Page 148: ...ACSIMILE CODED DATA BLOCK FCD AFTER 256 FRAMES TRANSMIT 3 TIMES FLAG ADDRESS FIELD CONTROL FIELD FCF FOR FCD FRAME NUMBER FACSIMILE DATA EOL TAG ALIGN BITS FCS CHECK FLAG OR 64 FCF FOR RCP FCS FLAG AC...

Page 149: ...T MESSAGE RX READY MESSAGE PAGE 1 BLOCK 0 PPS EOP INDICATES END OF PROCEDURE I E NO MORE PAGES TO TRANSMIT PPR INDICATES FRAME ERRORS RETRANSMIT MESSAGE FRAMES IN ERROR PAGE 1 BLOCK 0 PPS EOP PPR 4TH...

Page 150: ...R FIF FCS F PPS NUL EOP MPS EOM PAGE COUNT 0 255 BLOCK COUNT 0 255 TOTAL OF FRAMES IN BLOCK 1 256 FSK 300 BPS F FLAG A ADDRESS FIELD C CONTROL FIELD FCS FRAME CHECK SEQUENCE PPR FRAME STRUCTURE FCF FO...

Page 151: ...fax or voice message is being received is necessary for combined fax answering machines When configured for Voice Audio Codec mode decoding of an outgoing message three tone detectors are available T...

Page 152: ...ide 9 30 1070 FSK7E 08 2 1 PNSUC 08 3 1 INITIALIZE AND START TIMER1 Yes Yes No No Yes No 1070F9 26 START HIGH SPEED DETECTOR T 30 TIMEOUT ERROR FSK DETECTED RECONFIGURE TO FSK TIMER1 6 7 SEC Figure 9...

Page 153: ...ICIANTS FOR THE FSK 7E DETECTION INITIALIZE A TIMER T1 FOR FLAGS DETECTION TIME OUT INITIALIZE A TIMER T2 FOR DEBOUNCING FLAGS T1 EXPIRED FR1 O8 5 1 FR1 O8 5 1 1070F9 27 END No Yes T2 EXPIRED No No Ye...

Page 154: ...CTED 1ST CNG WAS DETECTED INITIALIZE TIMER 2 WITH CNG ON TIME MAX INITIALIZE TIMER2 WITH CNG OFF TIME MAX TIMER 2 TIME OUT TIMER2 TIME OUT TIMER 2 TIME OUT TIMER 1 TIME OUT 1070F9 28 EXIT No No No No...

Page 155: ...ly reset to 0 prior to the long train V 17 reception 1070F9 29 CALLING STATION Transmitting TCF long train V 17 Configure for FSK receiver Transmitting fax message short train V 17 CALLED STATION Rece...

Page 156: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 9 34 1070 This page intentionally left blank...

Page 157: ...1200 12 Hz Logical 0 space 2200 22 Hz Transmission Rate 1200 bps Transmission Level 13 5 1 dBm into 900 load 10 4 PROTOCOL The protocol uses 8 bit data words bytes each bounded by a start bit and a st...

Page 158: ...lly indicates that the message was correctly received Message retransmission is not supported Example CND Single Data Message An example of a received CND message beginning with the message type word...

Page 159: ...After a valid ring is detected the RI bit is set to indicate occurrence of the first ring burst to the host The host waits for 250 ms of silence then activates the CNDEN line see Figure 10 1 and conf...

Page 160: ...Guide 10 4 1070 Check_Ring Valid ring detected Start Caller_Id detection START_CALLER_ID Decrement the ring counter Ring count finished Start to receive the fax message RX_FAX End Y Y Printer Fault N...

Page 161: ...ize a 3 sec timer for Caller_id time out Enable CNDEN relay for Caller_Id detection Check if Time out Check if RSLD is on Read Data Buffer DBUFF 10 0 7 Read Data Buffer DBUFF 10 0 7 CHECK CALLER_ID SE...

Page 162: ...DBUFF 10 0 7 Indicate Caller_Id has an error End of Caller_Id message Store data into memory Calculate checksum Indicate caller_Id is done Checksum is correct Y Y End Call_Id N Check_Caller_Id Disabl...

Page 163: ...ient range is from 1 8000h to 1 minus 1 least significant bit 7FFFh The poles and zeros are shown in Table 11 1 The programmable digital equalizer RAM access codes are shown in Table 11 2 Note that th...

Page 164: ...ASS FILTER LOW PASS FILTER OPTIONAL HIGH PASS FILTER TONE DETECTOR OPTIONAL DIG CABLE EQUALIZER ENERGY DETECTOR OPTIONAL PROGRAM DIG EQUALIZER V 33 V 17 V 29 V 27 TER V 21 RECEIVER DATA OUTPUT CONTROL...

Page 165: ...NAL DIG CABLE EQUALIZER AUTOMATIC GAIN CONTROL V 33 V 17 V 29 V 27 TER V 21 RECEIVER DATA OUTPUT CONTROL INTEGRATED ANALOG DIGITAL SIGNAL PROCESSOR Figure 11 2 High Speed and V 21 Transmit Signal Path...

Page 166: ...70F11 4 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 2 3 4 1 2 1 1 1 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 0 2 0 3 0 1 2 3 4 Default Thousands FREQUENCY Hz Thousands...

Page 167: ...C000 0 50000000 a12 0 0 1 0 48 2 3 A8FF 0 67972752 a22 0 0 1 0 49 2 3 8000 1 00000000 a13 0 0 1 0 4A 2 3 EAD7 0 16531356 a23 0 0 1 0 4B 2 3 8000 1 00000000 a14 0 0 1 0 4C 2 3 291D 0 32118352 a24 0 0 1...

Page 168: ...4 S23 and RFX96V24 S23 Modem Designer s Guide 11 6 1070 0dB 20dB 40dB 60dB 80dB 100dB LOG MAGNITUDE dB VS FREQUENCY FREQUENCY HERTZ 0 40 80 120 160 200 Figure 11 6 Receive Path Frequency Response with...

Page 169: ...24 S23 and RFX96V24 S23 Modem Designer s Guide 1070 11 7 0dB 20dB 40dB 60dB 80dB 100dB LOG MAGNITUDE dB VS FREQUENCY FREQUENCY HERTZ 0 60 120 180 240 300 Figure 11 7 Receive Path Frequency Response wi...

Page 170: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 11 8 1070 This page is intentionally blank...

Page 171: ...gnaling tones such as dial tone Two programmable dual tone transmitters and one tone detector are supplied for these purposes 12 2 SPEAKERPHONE DESIGN A speakerphone design includes the speakerphone h...

Page 172: ...and frequency response be used as used in Figure 14 3 for normal 2 wire telephone interface 12 3 SPEAKERPHONE CONTROL While in configuration 91h the speakerphone control bits at interface register lo...

Page 173: ...each channel tone can be a single tone dual tone or melody ring tone Frequency and output level information for each desired tone from the IIA or XIA must be programmed prior to activation First the T...

Page 174: ...is volume control If signal overflow or underflow situation happens after applying the volume control gain the signal will be limited to 7FFFh or 8000h in the modem depending on the signal polarity Th...

Page 175: ...signal appropriately The AGC gain adaptation on the other hand is a slow rise and fast drop process The gain s rise time is controlled by the AGC slew rate The long term sample by sample averaged sig...

Page 176: ...gle bank memory values can be optimized to each specific language The default values are optimized for American English Minimum On Time ms Speech_hangover 8 When the local speech is detected the trans...

Page 177: ...x x x x x x Tone Transmit x Handset x x x x x x x x Microphone Mute x x x x x x Speaker Mute x x x x x x Notes 1 x means that the corresponding bit is active Table 12 2 Register Location 0F Use Bit TO...

Page 178: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 12 8 1070 This page is intentionally blank...

Page 179: ...oise ratio of 15 dB in the presence of 30 peak to noise phase jitter at 120 Hz At 4800 bps V 27 ter the modem exhibits a bit error rate of 10 6 or less with a signal to noise ratio of 19 dB in the pre...

Page 180: ...7 9 Required Cycle Time 93 0 1 0 ms Yes 2 3 4 5 6 7 9 Dynamic Range 43 0 0 0 dBm Yes 1 2 3 5 6 7 9 Signal to Noise Ratio 12 0 dB 1 2 3 4 5 6 7 9 Talk Off 2 3 Hits 8 9 Notes 1 On time 50 ms off time 5...

Page 181: ...35 00 68 70 54 80 44 20 35 50 28 40 7 60 8 90 3 00 3 70 9 60 4 80 6 10 11 15 12 20 14 00 7 75 15 40 19 90 9 80 12 35 22 45 19 40 24 20 27 90 V 29 9600 bps V 29 7200 bps V 27 4800 bps V 27 2400 bps a...

Page 182: ...57 70 45 80 29 30 18 85 7 70 3 70 36 50 4 80 9 70 12 40 6 00 23 70 15 80 7 90 16 50 30 50 20 50 V 33 14400 bps 1800 Hz V 33 12000 bps 1800 Hz TCM 9600 bps 1800 Hz TCM 7200 bps 1800 Hz b V 33 and TCM 1...

Page 183: ...30 57 30 45 60 36 30 14 80 7 80 3 70 18 80 4 75 23 70 9 80 6 00 30 30 12 50 7 90 10 20 16 00 20 80 V 33 14400 bps 1700 Hz V 33 12000 bps 1700 Hz TCM 9600 bps 1700 Hz TCM 7200 bps 1700 Hz c V 33 and TC...

Page 184: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 13 6 1070 This page intentionally left blank...

Page 185: ...correct for more than 99 8 of the units Figure 14 4 shows a recommended microphone circuit Figure 14 5 shows a typical speaker circuit The corresponding parts list is shown in Table 14 1 14 1 1 Cryst...

Page 186: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 14 2 1070 Figure 14 1 Recommended Modem Speakerphone Interface Circuit...

Page 187: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 1070 14 3 Figure 14 2 Typical Line Interface Circuit Figure 14 3 Typical Interface to External Hybrid...

Page 188: ...RFX144V24 S23 and RFX96V24 S23 Modem Designer s Guide 14 4 1070 Figure 14 4 Typical Microphone Circuit Figure 14 5 Typical Speaker Circuit...

Page 189: ...H 10 Y1 Crystal 49 92 MHz 53 76 MHz See Table 14 2 Typical Microphone Circuit See Figure 14 4 C3 Capacitor 33 pF 5 50V C2 C4 C6 Capacitor 0 1 F 10 50V C1 Capacitor 10 F 20 25V C5 Capacitor 20 F 20 25V...

Page 190: ...terface to Hybrid Circuit See Figure 14 3 C8 C9 Capacitor 1000 pF 5 25V C4 C5 Capacitor 0 22 F 10 25V C1 C2 C3 C6 C7 Capacitor 0 1 F 10 25V D1 D2 Zener Diode NLL5243B R8 Resistor 604 1 1 8W R5 R6 Resi...

Page 191: ...5 years Oscillation Mode Third overtone Third overtone Calibration Mode Parallel resonant Parallel resonant Load Capacitance C L 18 pF nom 18 pF nom Shunt Capacitance C O 6 pF max 6 pF max Series Resi...

Page 192: ...imizing on board noise EMI generation see next section 1 Place the MDP and XIA devices and all supporting analog circuitry including the DAA if required on the same area of PCB 2 All power traces shou...

Page 193: ...s 7 Decouple the power cord at the power cord interface with decoupling capacitors 8 Locate high frequency circuits in a separate area to minimize capacitive coupling to other circuits 9 Locate cables...

Page 194: ...29 38 40 Speaker Monitor Interface 44 Serial DTE Interface 67 68 99 100 MCU Interface 1 5 7 15 52 53 68 78 MDP Interconnect 75 76 93 39 40 XIA Interface 17 20 23 24 48 50 79 82 83 86 88 90 5VD 5VA 6 2...

Page 195: ...REF 18 85 REF 17 45 14 0 REF 12 35 REF 1 03 1 6 REF 0 65 BSC 0 45 0 19 0 10 MAX 0 0020 0 9035 0 6673 0 0287 0 0098 0 0051 A A1 A2 D D1 D2 E E1 E2 L L1 e b c Coplanarity Min Max Min Max Inches Dim Ref...

Page 196: ...IN 1 REF CHAM h x 45 DEG 3 PLCS CHAM J x 45 DEG Millimeters 4 19 0 432 12 32 10 41 4 72 0 508 REF 0 533 12 57 11 48 REF 7 62 REF 10 92 1 27 BSC 0 254 TYP 1 15 TYP 45 TYP 0 10 MAX 0 165 0 017 0 485 0 4...

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