RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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2-1
2. HARDWARE INTERFACE SIGNALS
The hardware interface signals are shown in Figure 2-1.
In Figure 2-1, any point that is active when exhibiting the relatively more negative voltage of a two-voltage system (e.g., 0
VDC for TTL or -12 VDC for EIA/TIA-232-E) is called active low and is represented by a small circle at the signal point.
Active low signals are indicated by a tilde (~), e.g., ~RESET. Edge-triggered clocks are indicated by a small triangle (e.g.,
DCLK). Open-collector (open-source or open-drain) outputs are denoted by a small half circle (e.g., signal ~IRQ1).
A clock intended to activate logic on its rising edge (low-to-high transition) is called active low, while a clock intended to
activate logic on its falling edge (high-to-low transition) is called active high. When a clock input is associated with a small
circle, the input activates on a falling edge. If no circle is shown, the input activates on a rising edge.
The MDP pin assignments are shown in Figure 2-2 and hardware interface signals are listed by pin number in Table 2-1.
The XIA pin assignments are shown in Figure 2-3 and hardware interface signals are listed by pin number in Table 2-2.
The MDP hardware interface signals are defined in Table 2-3.
The XIA hardware interface signals are defined in Table 2-4.
Digital signal interface characteristics are defined in Table 2-5.
Analog signal interface characteristics are defined in Table 2-6.
Power consumption is listed in Table 2-7.
Absolute maximum ratings are specified in Table 2-8.
The microprocessor host bus interface waveforms are illustrated in Figure 2-4. The microprocessor host bus timing is listed
in Table 2-9.
The serial DTE interface waveforms are illustrated in Figure 2-5 and Figure 2-6.
The eye pattern waveforms are illustrated in Figure 2-7. A schematic for an eye pattern generator circuit is shown in Figure
2-8.
Summary of Contents for RFX144V24-S23
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