74
6.X Ladder instructions descriptions
6.1 Bit logic
6.1.1 Normally open and normally closed
Input / output
Operand
Data type
Bit
(
LAD
、
STL
)
I, Q, M, SM, T, C, V, S, L
Boolean
Input
(
FBD
)
I, Q, M, SM, T, C, V, S, L, Enable bit
Boolean
Output
(
FBD
)
I, Q, M, SM, T, C, V, S, L, Enable bit
Boolean
Summary of Contents for PR-12 Series
Page 26: ...19 1 xLogic CPU PR 12 Series CPU PR 14 and PR 18 series 1 PR 18 CPU 2 PR E extension...
Page 27: ...20 PR 24 series...
Page 47: ...40 5 3 Instruction tree...
Page 58: ...51 5 3 10 Instructions Instructions will be explained in detail in the instructions section...
Page 93: ...86 2 Enter the illegal real number Example...
Page 127: ...120 Example...
Page 139: ...132 Special memory bit SM1 0 Zero result SM1 1 overflow SM1 2 Negative result Example...
Page 149: ...142 Example...
Page 152: ...145 Example ATCH instruction only needs to be connected once...
Page 154: ...147 Example...
Page 175: ...168...
Page 217: ...210 Example Four arithmetic operation Main program...
Page 218: ...211 Subroutine...
Page 252: ...245 10 8 Example of serial port free port communication Program 1...
Page 254: ...247 10 9 Example of CAN free port...
Page 258: ...251 Conversion of Process quantity and set value unit...