74
High-speed Counter Board
Section 2-1
Lower and upper limits for ranges 1 through 16 and bit patterns 1 through 16
are registered in the range comparison table. Of bits 0 to 11 of each of these
bit patterns, bits 0 to 7 are stored as internal output bits, and bits 8 to 11 are
stored as external output bits. As shown in the diagram below, the bits in the
external bit pattern are used in an OR operation on the corresponding bits of
high-speed counters 1 to 4, the results of which are then output as external
outputs 1 to 4.
PV of high-speed counter
Comparison
Lower limit 1 to upper limit 1
Bit pattern 1
External
output bits
An OR is taken of
corresponding bits
of IR 208 to IR 211,
or IR 240 to IR 243.
External outputs
(four outputs)
Internal output
bits (8 bits)
Lower limit 2 to upper limit 2
Lower limit 16 to upper limit 16
Bit pattern 2
Bit pattern 16
IR 208 to IR 211 or
IR 240 to IR 243
Bit pattern output when PV is inside a range.
Comparison table
Comparison range 1
Comparison range 2
Comparison range 3
Comparison range 4
Comparison range 4
Comparison range 3
Comparison range 2
Comparison range 1
Counter PV
The PV is continually compared to all comparison ranges.
Time (s)
Bit pattern output to memory
High-speed counter 1 comparison result (IR 208 or IR 240)
High-speed counter 2 comparison result (IR 209 or IR 241)
High-speed counter 3 comparison result (IR 210 or IR 242)
High-speed counter 4 comparison result (IR 211 or IR 243)
Slot 1
Slot 2
Bit
Example:
External output 1 ON
External output 2 ON
External output 3 ON
External output 4 OFF
An OR is taken of the bits in
the same position and the
result is output.
