496
Cycle Time
Section 7-3
High-speed timers: The time shown below is required, depending on (a) the
number of timers used with TIMH(15) and (b) the number
of high-speed timers active at that time. (The number of
high-speed timers is set in the PC Setup, DM 6629. The
default setting is 16.)
0
≤
Standby time
≤
40 + 3
×
(a + b)
µ
s
Up to 40
µ
s can be required even when no high-speed
timers are used.
Generation and clearing of non-fatal errors:
When a non-fatal error is generated and the error contents
are registered at the CQM1H, or when an error is being
cleared, interrupts will be masked for a maximum of 75
µ
s
until the processing has been completed.
Online editing: Interrupts will be masked for a maximum of 250 ms when
online editing is executed during operation.
Pulse output based on SPED(64) may also be affected by interrupt process-
ing, thus causing output timing to vary.
Example Calculation
This example shows the interrupt response time (i.e., the time from when the
interrupt input turns ON until the start of the interrupt processing routine)
when input interrupts are used under the conditions shown below.
Number of high-speed timers: 0 (No high-speed timers started)
Online edit:
Not used
Input refresh at interrupt:
No
Minimum Response Time
Interrupt input ON delay:
100
µ
s
Interrupt mask standby time:
0
µ
s
+
Change-to-interrupt processing: 30
µ
s
Minimum response time:
130
µ
s
Maximum Response Time
Interrupt input ON delay:
100
µ
s
Interrupt mask standby time:
40
µ
s
+
Change-to-interrupt processing: 30
µ
s
Minimum response time:
170
µ
s
In addition to the response time shown above, the time required for executing
the interrupt processing routine itself and a return time of 30
µ
s must also be
accounted for when returning to the process that was interrupted.
Be sure to allow for interrupt processing time when using interrupts in the pro-
gram.
Outputs from interrupt routines can be output immediately if direct output is
used. Direct output will be used for both the main program and the interrupt
routines, and cannot be set separately.
