19
Interrupt Functions
Section 1-4
Note
Interrupt processing is not performed for high-speed counters 1, 2, 3, and 4
on a High-speed Counter Board. A High-speed Counter Board can count
pulses up to 50 kHz or 500 kHz. The high-speed counter PVs can be checked
against a target value or an SV range and a bit pattern can be output inter-
nally or externally instead of generating an interrupt.
Serial Communications Board Interrupts:
Interrupt processing is requested from the CPU Unit when the Serial Commu-
nications Board receives the desired message.
Interrupt Processing
When an interrupt is generated, the specified interrupt subroutine is executed.
Defining Subroutines
Just as with ordinary subroutines, interrupt subroutines are defined using
SBN(92) and RET(93) at the end of the main program.
When interrupt subroutines are executed, a specified range of input bits can
be refreshed.
When an interrupt subroutine is defined, a “no SBS error” will be generated
during the program check but execution will proceed normally. If this error
occurs, check all normal subroutines to be sure that SBS(91) has been pro-
grammed before proceeding.
Interrupt Priority
Interrupts have the following order of priority. Input interrupts and interrupts
from high-speed counters 1 and 2 have the highest priority and the interrupt
notification from a Serial Communications Board has the lowest.
When an interrupt with a higher priority is received during interrupt process-
ing, the current processes will be stopped and the newly received interrupt will
be processed instead. After that routine has been completely executed, then
processing of the previous interrupt will be resumed.
When an interrupt with a lower or equal priority is received during interrupt
processing, then the newly received interrupt will be processed as soon as the
routine currently being processed has been completely executed.
If two interrupts with the same priority level occur simultaneously, the inter-
rupts will be executed in the following order:
1,2,3...
1.
Input interrupt 0 > Input interrupt 1 > Input interrupt 2 > Input interrupt 3
> High-speed counter interrupt 1 > High-speed counter interrupt 2
2.
Interval timer interrupt 0 > Interval timer interrupt 1 > Interval timer interrupt
2 (Interval timer interrupt 2 is high-speed counter interrupt 0.)
Pulse Output Instructions
and Interrupts
The following instructions cannot be executed in an interrupt subroutine when
an instruction that controls pulse I/O or high-speed counters is being executed
in the main program: (SR 25503 turns ON)
INI(89), PRV(62), CTBL(63), SPED(64), PULS(65), PWM(––), PLS2(––)
and ACC(––)
Input
interrupts
=
High-speed counter
1 or 2 interrupts
(from Pulse I/O
Board or Absolute
Encoder Interface
Board)
Interval timer
interrupts
>
=
High-speed
counter 0
interrupt
Interrupt
notification from
Serial
Communications
Board
>
