NEC PD78212, User Manual

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18
CHAPTER 18 INSTRUCTION OPERATIONS
This chapter describes the operation of each instruction of the
µ
PD78214 sub-series. Refer to the 78K/II Series
User’s Manual, Instructions (IEU-1311) for details of each operation, the corresponding machine language code
(instruction code), and the number of clock states for each instruction.
18.1 LEGEND
18.1.1 Operand Field
Code operands in the operand field for each instruction, using the specified operand representation format (for
details, refer to the relevant assembler specifications). When several coding forms are presented, any one can be
used. Since uppercase letters and s, –, #, !, $, /, [], and & are keywords, write any symbols as is.
Do not omit s, –, #, !, $, /, [], and & when writing immediate data with labels. r and rp can be written with
any functional and absolute names.
+ : Auto increment
– : Auto decrement
# : Immediate data
! : Absolute addressing
$ : Relative addressing
/ : Bit inversion
[] : Indirect addressing
& : Sub-bank specification
r,r’ : Registers;
Functional name : X, A, C, B, E, D, L, H
Absolute name : R0-R7
r1 : Register group 1;
B, C
rp, rp’ : Register pairs;
Functional name : AX, BC, DE, HL
Absolute name : RP0-RP3
sfr : Special function registers;
P0, P2, P3, P4, P5, P6, P7, P0H, P0L, RTPC, CR10, CR11, CR20, CR21, CR22, CR30, PM0, PM3, PM5, PM6,
PMC3, PUO, CRC0, CRC1, CRC2, TOC, TM1, TM2, TM3, TMC0, TMC1, PRM0, PRM1, ADM, ADCR, CSIM,
SBIC, SIO, ASIM, ASIS, RXB, TXS, BRGC, STBC (only for dedicated instruction), MM, PW, RFM, IF0L, IF0H,
MK0L, MK0H, PR0L, PR0H, ISM0L, ISM0H, INTM0, INTM1, IST
sfrp : Special function register pairs;
CR00, CR01, CR02, TM0, IF0, MK0, PR0, ISM0
mem : Memory address indicated in indirect addressing mode;
Register indirect mode : [DE], [HL], [DE+], [HL+], [DE–], [HL–]
Base mode : [DE+byte], [HL+byte], [SP+byte]
Indexed mode : word[A], word[B], word[DE], word[HL]
mem1 : Memory address indicated in indirect addressing group 1 mode;
[DE], [HL]