NEC PD78212, User Manual

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228
µ
PD78214 Sub-Series
(7) Edge detector
The edge detector detects the valid edge of an input at the interrupt request input pin (INTP5) and generates
an external interrupt request signal (INTP5) and an external trigger for A/D conversion.
The valid edge of an input at the INTP5 pin is specified by external interrupt mode register 1 (INTM1) (see Fig.
11-2 ). The external trigger is enabled or disabled by the ADM register (see Section 8.2 ).
8.2 A/D CONVERTER MODE REGISTER (ADM)
This 8-bit register controls A/D converter operations.
A bit manipulation instruction or an 8-bit manipulation instruction can be used to read data from or write data to
this register. Fig. 8-3 shows the ADM format.
Bit 0 (MS) of the ADM register controls the A/D converter operating mode.
Bits 1, 2, and 3 (ANI0, ANI1, and ANI2) select analog input signals to be converted to digital form.
Bit 6 (TRG) is used to enable external synchronization for A/D conversion. When the TRG bit is set to 1, if the CS
bit is already 1, the conversion is initialized each time a valid edge arrives at the INTP5 pin as an external trigger.
When the TRG bits is reset to 0, conversion is carried out regardless of the state of the INTP5 pin.
Bit 7 (CS) controls A/D conversion. When this bit is set to 1, the A/D converter starts operating. When the CS bit
is reset to 0, the converter stops, even if it is in the middle of conversion. At this point, however, the ADCR register
contents are not updated, nor does an INTPAD interrupt occurs. Power supply to the voltage comparator is
stopped to reduce supply current to the A/D converter.
When the RESET signal is input, the ADM register is reset to 00H.
Caution When using the STOP mode, reset the CS bit to 0 beforehand to reduce supply current. If the CS bit remains set to 1, conversion
do stops when the STOP mode is selected, but power supply to the voltage comparator is not stopped. Consequently, the supply
current to the A/D converter does not decrease.