NEC PD78212, User Manual

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Chapter 10 Clock Synchronous Serial Interface
10
10.4.2 Operation When Only Transmission Is Permitted
Transmission is enabled when the CTXE bit of the clock synchronous serial interface mode register (CSIM) is set
(1). If the CTXE bit is set, writing the contents of the shift register (SIO) invokes the start of transmission.
If the CTXE bit is reset (0), the output from the SO pin goes to the high-impedance state.
(1) Selecting the internal clock as the serial clock
When transmission is started, the serial clock is output from the SCK pin. At the same time, data is sequentially
output from the SIO to the SO pin in synchronization with the falling edge of the serial clock. In synchronization
with the rising edge of the serial clock, the signal from the SI pin is shifted into the SIO.
It takes up to one cycle of the SCK clock to drive SCK low for the first time after transmission is started.
If transmission is inhibited (the CTXE bit is reset to 0) during transmission, the output of the SCK clock is
stopped and transmission is halted at the next rising edge of SCK. At this time, no interrupt request (INTCSI)
occurs. The output from the SO pin goes to the high-impedance state.
(2) Selecting the external clock as the serial clock
When transmission is started, data is sequentially output from the SIO to the SO pin in synchronization with
the falling edge of the serial clock input to the SCK pin, after the start of transmission. At the same time, the
signal from the SI pin is shifted into the SIO in synchronization with the rising edge of the input to the SCK
pin. If the serial clock is input to the SCK pin before transmission has been started, no shift occurs. The output
level of the SO pin does not change.
If transmission is inhibited (the CTXE bit is reset to 0) during transmission, the transmission is halted and any
subsequent SCK input is ignored. At this time, no interrupt request (INTCSI) occurs. The output from the SO
pin goes to the high-impedance state.
10.4.3 Operation When Only Reception Is Permitted
Reception is performed when the CRXE bit of the CSIM register is set (1). When the CRXE bit is changed from 0
to 1 or when the contents of the SIO are read, reception is started.
(1) Selecting the internal clock as the serial clock
When reception is started, the serial clock is output from the SCK pin. In synchronization with the rising edge
of the serial clock, data is sequentially sent from the SI pin to the SIO.
It takes up to one cycle of the SCK clock to drive SCK low for the first time, after the reception is started.
If reception is inhibited (the CRXE bit is reset to 0) during reception, the output of the SCK clock is stopped
and reception is halted at the next rising edge of SCK. At this time, no interrupt request (INTCSI) is issued.
The contents of the SIO become undefined.
(2) Selecting the external clock as the serial clock
When reception is started, data is sent sequentially from the SI pin to the SIO in synchronization with the rising
edge of the serial clock input to the SCK pin after the start of reception. If the serial clock is input to the SCK
pin before reception has been started, no shift occurs.
If reception is inhibited (the CRXE bit is reset to 0) during reception, the reception is halted and subsequent
SCK input is ignored. At this time, no interrupt request (INTCSI) is issued.
10.4.4 Operation When Both Transmission and Reception Are Permitted
Transmission and reception can be simultaneously performed when both the CTXE bit and CRXE bit of the CSIM
register are set (1) (transmission and reception). Transmission and reception are started when the CRXE bit is
changed from 0 to 1 or when the contents of the SIO are written.
When transmission and reception are started for the first time, the CRXE bit is changed from 0 to 1. Because
transmission and reception are started immediately, undefined data may be output. To prevent this, write the first
transmission data into the SIO while both transmission and reception are inhibited (the CTXE and CRXE bits are
both reset to 0), then permit transmission and reception.
If transmission and reception are inhibited (both CTXE and CRXE are set to 0), the output from the SO pin goes
to the high-impedance state.