NEC PD78212, User Manual

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308
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PD78214 Sub-Series
12.2.6 Program Status Word (PSW)
The PSW is a register that holds the result of instruction execution and the current status of interrupt requests. The
register is mapped with the IE flag that specifies whether to enable maskable interrupts and the ISP flag to control
multiple-interrupt handling.
The PSW can be read and written to in 8-bit units. It can also be manipulated by a bit manipulation instruction and
dedicated instructions (EI and DI). When a vectored interrupt request is accepted, and the BRK instruction is
executed, the PSW is saved in the stack, and the IE flag is reset to 0. When a maskable interrupt request is accepted,
the priority specification flag for the corresponding interrupt is transferred to the ISP flag. When a nonmaskable
interrupt request is accepted, the ISP flag is reset to 0. Also when the PUSH PSW instruction is executed, the PSW
is saved in the stack. Executing the RETI, RETB, or POP PSW instruction restores the PSW from the stack.
When the RESET signal is input, the PSW is set to 02H.
Fig. 12-8 Program Status Word Format
Priority for interrupt currently processed ISP
Interrupt with higher priority is processed
(low-priority interrupt is disabled).
0
Interrupt is not accepted, or low-priority interrupt
is processed (all maskable interrupts are enabled).
1
IE
7
Z
6
RBS1
5
AC
4
RBS0
3
0
2
ISP
1
CY
0
PSW
Used when ordinary instruction is executed
Enables or disables interrupts IE
Disables 0
Enables 1
12.3 INTERRUPT HANDLING
12.3.1 Accepting Software Interrupts
A software interrupt request is accepted by executing the BRK instruction. Software interrupts cannot be disabled.
When a software interrupt request is accepted, the PSW and PC are saved in the stack in the stated order, the IE
flag is reset to 0, and the PC is loaded with the contents of the vector table (at 003EH and 003FH) to cause a branch.
The RETB instruction is used to return from software interrupt handling.
Caution Do not use the RETI instruction to return from software interrupt handling.
12.3.2 Accepting Nonmaskable Interrupts
A nonmaskable interrupt request is accepted regardless of whether interrupts are enabled. It is not subjected to
priority control. Instead it has precedence over all other interrupt requests.
When a nonmaskable interrupt request is accepted, the NMIS bit of the interrupt status register (IST) is set to 1,
the PSW and PC are saved in the stack in the stated order, the IE and ISP flags are reset to 0, and the PC is loaded
with the contents of the vector table to cause a branch. When the RETI instruction is executed, the NMIS bit is reset
to 0.
If the NMIS bit is 1, a new nonmaskable interrupt request is not accepted. It is kept pending until the NMIS bit is
reset to 0. In other words, when a nonmaskable interrupt service program is running, a new nonmaskable interrupt
request is not accepted. If a new nonmaskable interrupt request occurs when a nonmaskable interrupt service
program is already running, it is accepted after the service program ends (an RETI instruction is executed). In this
case, if two nonmaskable interrupt requests occur, only one request is accepted after the current service program
ends.