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390

µ

PD78214 Sub-Series

Table 15-1 Pin States during Reset and After Reset State Is Released

Pin name

P00-P07

P20/NMI-27/SI

P30/RxD-P37/TO3

P40/AD0-P47/AD7

P50/A8-P57/A15

P60/A16-P63/A19

P64/RD, P65/WR

P66/WAIT/AN6, P67/REFRQ/AN7

P70/AN0-P75/AN5

ASTB

I/O

Output

Input

I/O

I/O

I/O

Output

I/O

I/O

Input

Output

During reset

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

After reset state is released

Hi-Z

Hi-Z (input port)

Hi-Z (input port mode)

Hi-Z (input port mode)

Note

Hi-Z (input port mode)

Note

0

Hi-Z (input port mode)

Note

Hi-Z (input port mode)

Hi-Z (input port mode)

0

Note

When ROM-less mode is specified (EA pin = 0), these pins function as an address/data bus and output signals for fetching the reset vector
address from address 0000H (see

Fig. 15-3 (a)

).

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Summary of Contents for PD78212

Page 1: ...S 8 BIT SINGLE CHIP MICROCOMPUTER HARDWARE µPD78212 µPD78213 µPD78214 µPD78P214 µPD78212 A µPD78213 A µPD78214 A µPD78P214 A Document No IEU 1236H O D No IEM 5119H Date Published September 1994 P Printed in Japan NEC Corporation 1989 ...

Page 2: ...AL INTERFACE CLOCK SYNCHRONOUS SERIAL INTERFACE EDGE DETECTION FUNCTION LOCAL BUS INTERFACE FUNCTION 13 12 11 10 17 16 15 14 C B A 18 INTERRUPT FUNCTIONS STANDBY FUNCTION RESET FUNCTION APPLICATION EXAMPLES PROGRAMMING FOR THE µPD78214 78K II SERIES PRODUCT LIST DEVELOPMENT TOOLS SOFTWARE FOR EMBEDDED APPLICATIONS REGISTER INDEX INDEX INSTRUCTION OPERATIONS D E ...

Page 3: ...ns may function as output pins at unexpected times each unused pin should be separately connected to the VDD or GND pin through a resistor If handling of unused pins is documented follow the instructions in the document 3 Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on Since characteristics of a MOS device are determ...

Page 4: ...der any patents copyrights or other intellectual property rights of NEC Corporation or others The devices listed in this document are not suitable for use in aerospace equipment submarine cables nuclear reactor control systems and life support systems If customers intend to use NEC devices for above applications or they intend to use Standard quality grade NEC devices for applications not intended...

Page 5: ...ollows IBM PC series has been changed to IBM PC AT Upgraded versions of MS DOS are now supported by some development tools designed for the PC 9800 series 3 5 2HC has been added to as a PC DOS distribution media MS DOS and IBM DOS have been added as supported operating systems for the IBM PC AT The description of real time OS has been deleted P 441 Appendix C has been added Major changes in this r...

Page 6: ...ted at the end of the chapter Be careful to observe these notes when using the products Guidance Readers of this manual are assumed to have a general knowledge of electronics logical circuits and microcom puters When using this manual with the µPD78212 µPD78213 µPD78P214 µPD78212 A µPD78213 A µPD78214 A or µPD78P214 A ThismanualdescribesthefunctionsoftheµPD78212 µPD78213 µPD78214 µPD78P214 µPD7821...

Page 7: ...the chapter related to the erroneous function To become familiar with the general functions of the µPD78214 sub series Read the entire manual in the order of the table of contents To determine the instructions supported by the µPD78214 sub series in detail Refer to 78K II Series User s Manual Instruction IEU 1311 To determine the electrical characteristics of the µPD78214 sub series Refer to the s...

Page 8: ...tion Floating Point Arithme tic Operation Programs µPD78212 A µPD78213 A µPD78214 A µPD78P214 A This manual IEU 1311 IEA 1220 IEA 1282 IEA 1273 IC 2526 IC 2831 IC 3095 B 7 1 6 0 5 4 A 3 1 2 0 1 0 EDC Write operation Read operation The encircled bit number indicates that the bit name is used as reserved word by the NEC assembler and defined by the header file sfrbit h by C compiler Either 0 or 1 ca...

Page 9: ... Fuzzy Inference Module Translator User s Manual for Tool for Creating Fuzzy Knowledge Data 78K 0 78K II and 87AD Series Fuzzy Inference Development Support System User s Manual IE 78240 R A In Circuit Emulator User s Manual IE 78240 R In Circuit Emulator User s Manual Hardware Software IE 78210 R In Circuit Emulator Hardware Operator s Manual IE 78210 R In Circuit Emulator Software Operator s Man...

Page 10: ...urface Mount Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability Quality Control System Guide to Quality Assurance for Semiconductor Devices Caution The above documents may be revised without notice Use the latest versions when you designing an application system ...

Page 11: ......

Page 12: ...µPD78P214 A 22 1 12 DIFFERENCES BETWEEN THE µPD78212 µPD78213 µPD78214 AND µPD78P214 23 1 12 1 Functional Differences 23 1 12 2 Package Differences 23 CHAPTER 2 PIN FUNCTIONS 25 2 1 PIN FUNCTION LIST 25 2 1 1 Normal Operating Mode 25 2 1 2 PROM Programming Mode 27 2 2 PIN FUNCTIONS 27 2 2 1 Normal Operating Mode 27 2 2 2 PROM Programming Mode 31 2 3 I O CIRCUITS AND UNUSED PIN HANDLING 33 2 4 NOTE...

Page 13: ... 4 PORT 3 66 5 4 1 Hardware Configuration 68 5 4 2 Setting the I O Mode and Control Mode 71 5 4 3 Operation 73 5 4 4 Built In Pull Up Resistor 74 5 5 PORT 4 75 5 5 1 Hardware Configuration 76 5 5 2 Setting the I O Mode and Control Mode 76 5 5 3 Operation 77 5 5 4 Built In Pull Up Resistor 78 5 5 5 Driving LEDs Directly 79 5 6 PORT 5 80 5 6 1 Hardware Configuration 80 5 6 2 Setting the I O Mode and...

Page 14: ...7 2 8 BIT TIMER COUNTER 1 139 7 2 1 Functions 139 7 2 2 Configuration 140 7 2 3 8 Bit Timer Counter 1 Control Registers 143 7 2 4 Operation of 8 Bit Timer 1 TM1 145 7 2 5 Compare Register and Capture Compare Register Operations 148 7 2 6 Sample Applications 151 7 3 8 BIT TIMER COUNTER 2 159 7 3 1 Functions 159 7 3 2 Configuration 161 7 3 3 8 Bit Timer Counter 2 Control Registers 163 7 3 4 Operatio...

Page 15: ... CONTROL REGISTER 245 9 3 ASYNCHRONOUS SERIAL INTERFACE OPERATIONS 247 9 3 1 Data Format 247 9 3 2 Parity Types and Operations 247 9 3 3 Transmission 248 9 3 4 Reception 249 9 3 5 Reception Error 249 9 4 BAUD RATE GENERATOR 251 9 4 1 Configuration of the Baud Rate Generator for UART 251 9 4 2 Baud Rate Generator Control Register BRGC 251 9 4 3 Operation of the Baud Rate Generator for UART 253 9 5 ...

Page 16: ...ion 287 10 6 9 Releasing the Busy State 287 10 6 10 Setting Wake Up 287 10 6 11 Starting Transmission and Reception 287 10 7 NOTES 292 CHAPTER 11 EDGE DETECTION FUNCTION 293 11 1 EXTERNAL INTERRUPT MODE REGISTERS INTM0 INTM1 293 11 2 EDGE DETECTION ON PIN P20 296 11 3 EDGE DETECTION ON PINS P21 TO P26 297 11 4 NOTES 298 CHAPTER 12 INTERRUPT FUNCTIONS 301 12 1 INTERRUPT REQUEST SOURCES 302 12 1 1 S...

Page 17: ...rnal Memory Expansion Function 347 13 2 2 1M Byte Expansion Function 348 13 2 3 Memory Mapping with Expanded Memory 350 13 2 4 Example of Connecting Memories 355 13 3 INTERNAL ROM HIGH SPEED FETCH FUNCTION 357 13 4 WAIT FUNCTION 357 13 5 PSEUDO STATIC RAM REFRESH FUNCTION 367 13 5 1 Function 367 13 5 2 Refresh Mode Register RFM 367 13 5 3 Operation 368 13 5 4 Example of Connecting Pseudo Static RA...

Page 18: ...ING TYPE 416 APPENDIX A 78K II SERIES PRODUCT LIST 421 APPENDIX B DEVELOPMENT TOOLS 429 B 1 HARDWARE 431 B 2 SOFTWARE 433 B 2 1 Language Processing Software 433 B 2 2 Software for the In Circuit Emulator 435 B 2 3 Software for the PROM Programmer 437 B 2 4 OS for the IBM PC 437 B 3 UPGRADING OTHER IN CIRCUIT EMULATORS TO 78K II SERIES LEVEL 438 B 3 1 Upgrading to IE 78240 R A Level 438 B 3 2 Upgra...

Page 19: ...llator 57 4 5 Incorrect Oscillator Connections 57 5 1 Port Configuration 59 5 2 Configuration of Port 0 61 5 3 Port 0 Mode Register Format 61 5 4 Port Specified as an Output Port 62 5 5 Example of Driving a Transistor 62 5 6 Block Diagram of Port 2 64 5 7 Port Specified as an Input Port 65 5 8 Built In Pull Up Resistor Format 65 5 9 Connection of Pull Up Resistors Port 2 66 5 10 Block Diagram of P...

Page 20: ...rol Register RTPC Format 97 6 3 Configuration of the Buffer Registers P0H and P0L 97 6 4 Real Time Output Port Operation Timing 100 6 5 Real Time Output Port Operation Timing Controlling 2 Channels Independently of Each Other 101 6 6 Real Time Output Port Operation Timing 102 6 7 Contents of the Control Register for the Real Time Output Function 103 6 8 Real Time Output Function Setting Procedure ...

Page 21: ...ng of Control Registers for PWM Output Operation 135 7 37 Setting Procedure for PWM Output 136 7 38 Changing Duty Factor of PWM Output 136 7 39 Example of PPG Signal Output by 16 Bit Timer Counter 137 7 40 Setting of Control Registers for PPG Output Operation 137 7 41 Setting Procedure for PPG Output 138 7 42 Changing Duty Factor of PPG Output 138 7 43 Block Diagram of 8 Bit Timer Counter 1 141 7 ...

Page 22: ... Shot Timer Operation 175 7 80 Compare Operation 176 7 81 TM2 Cleared After a Coincidence Is Detected 177 7 82 Capture Operation 178 7 83 TM2 Cleared After Capture Operation 179 7 84 Toggle Output Operation 181 7 85 PWM Pulse Output 182 7 86 Example of PWM Output Using TM2 183 7 87 PWM Output When CR20 FFH 184 7 88 Example of Rewriting a Compare Register 184 7 89 Example of PWM Output Signal with ...

Page 23: ...ompare Register CR30 209 7 127 Clear Operation When the CE3 Bit Is Reset to 0 209 7 128 Compare Operation 211 7 129 Timing of Interval Timer Operation 211 7 130 Setting of Control Registers for Interval Timer Operation 212 7 131 Setting Procedure for Interval Timer Operation 212 7 132 Count Start Operation 214 7 133 Count Operation Stop 214 7 134 Timing of Count Operation Stop and Restart 214 7 13...

Page 24: ...Serial Interface Mode Register CSIM 262 10 3 Format of Serial Bus Interface Control Register SBIC 264 10 4 Sample System Configuration with Three Wire Serial I O 265 10 5 Timing in Three Wire Serial I O Mode 266 10 6 Sample Connection with a Device Having Two Wire Serial I O 266 10 7 Sample Serial Bus Configured with SBI 269 10 8 Pin Configuration 270 10 9 Block Diagram of Clock Synchronous Serial...

Page 25: ...d Configuration 322 12 17 Macro Service Mode Register Format 323 12 18 Flow of Data Transfer by Macro Service Type A 325 12 19 Type A Macro Service Channel 326 12 20 Asynchronous Serial Reception 327 12 21 Flow of Data Transfer by Macro Service Type B 328 12 22 Type B Macro Service Channel 329 12 23 Parallel Data Input in Synchronization with an External Interrupt 330 12 24 Parallel Data Input Tim...

Page 26: ...20 Pulse Refresh When External Memory Is Accessed 369 13 21 Restoration Timing from Self Refresh 370 13 22 Return from Self Refresh 371 13 23 Example of Connecting Pseudo Static RAM to µPD78214 372 13 24 Return from Self Refresh 374 13 25 Glitch Observed on Pins A16 to A19 during Emulation 374 13 26 Insufficient Address Hold Time during Emulation 374 13 27 Preventing Problems That May Occur during...

Page 27: ... xvi Contents 17 1 Timing Chart for PROM Write and Verify 400 17 2 Write Operation Flowchart 401 17 3 PROM Read Timing Chart 402 Fig No Title Page ...

Page 28: ...ntervals of 16 Bit Timer Counter 109 7 3 Programmable Square Wave Output Setting Range of 16 Bit Timer Counter 109 7 4 Pulse Width Measurement Range of 16 Bit Timer Counter 109 7 5 Timer Output TO0 TO1 Operation 120 7 6 TO0 and TO1 Toggle Output 121 7 7 PWM Output on TO0 and TO1 122 7 8 PPG Output on TO0 125 7 9 Intervals of 8 Bit Timer Counter 1 139 7 10 Pulse Width Measurement Range of 8 Bit Tim...

Page 29: ... Requests That Can Specify Macro Service and Related SFRs Type A 324 12 9 Illegal Write Access Conditions and Corresponding Operations 324 12 10 Interrupt Requests That Can Specify Macro Service and SFRs Type C 331 12 11 Illegal Write Access Conditions and Corresponding Operations 331 12 12 Illegal Write Access Conditions and Corresponding Operations 344 13 1 Conditions and Operations for Illegal ...

Page 30: ...f the µPD78214 µPD78P214DW Programs can be written repeatedly suitable for evaluating an application system Others A program can be written once suitable for application systems produced in small lots TheµPD78212 A µPD78213 A µPD78214 A andµPD78P214 A are the special quality versions of theµPD78212 µPD78213 µPD78214 and µPD78P214 respectively PD78P214 PD78P214 A µ µ PD78214 PD78214 A µ µ PD78213 P...

Page 31: ...he macro service and timer counter are enhanced PD78224 sub series µ PD78214 sub series µ PD78244 sub series µ PD78218A sub series µ The A D converter is contained The timer counter and baud rated generator function are enhanced The comparator is deleted The internal memory is expanded The macro service and timer counter are enhanced EEPROM is added The macro service and timer counter are enhanced...

Page 32: ...14 RAM 512 bytes µPD78213 µPD78214 and µPD78P214 or 384 bytes µPD78212 Number of I O pins 54 µPD78212 µPD78214 and µPD78P214 or 36 µPD78213 Number of pins with software programmable pull up resistors 16 µPD78213 only or 34 other than µPD78213 Number of LED direct drive pins 16 µPD78212 µPD78214 and µPD78P214 Number of transistor direct drive pins 8 Serial interface UART baud rate generator include...

Page 33: ...PROM µPD78P214CW Note 64 pin plastic shrink DIP 750 mil Program written one time PROM µPD78P214GC AB8Note 64 pin plastic QFP 14 14 mm Program written one time PROM µPD78P214GJ 5BJNote 74 pin plastic QFP 20 20 mm Program written one time PROM µPD78P214GQ 36Note 64 pin plastic QUIP Program written one time PROM µPD78P214L Note 68 pin plastic QFJ Program written one time PROM µPD78212CW A 64 pin plas...

Page 34: ... Standard µPD78P214GC AB8Note 64 pin plastic QFP 14 14 mm Standard µPD78P214GJ 5BJNote 74 pin plastic QFP 20 20 mm Standard µPD78P214GQ 36Note 64 pin plastic QUIP Standard µPD78P214L Note 68 pin plastic QFJ Standard µPD78212CW A 64 pin plastic shrink DIP 750 mil Special µPD78212GC A AB8 64 pin plastic QFP 14 14 mm Special µPD78213CW A 64 pin plastic shrink DIP 750 mil Special µPD78213GQ A 36 64 pi...

Page 35: ...4 ASCK P24 INTP3 P23 INTP2 CI P22 INTP1 P21 INTP0 P20 NMI ASTB P40 AD0 P41 AD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P03 P04 P05 P06 P07 P67 REFRQ AN7 P66 WAIT AN6 P65 WR P64 RD P63 A19 P62 A18 P61 A17 P60 A16 RESET X2 X1 VSS P57 A15 P56 A14 P55 A13 P54 A12 P53 A11 P52 A10 P51 A9 P50 A8 P47 AD7 P46 AD6 P45 AD5 P44 AD4 P43 AD3 P42 AD2 VSS PD...

Page 36: ...TP2 CI P22 INTP1 P21 INTP0 P20 NMI ASTB P40 AD0 P41 AD1 VSS VSS P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 AD7 P50 A8 P71 AN1 P72 AN2 P73 AN3 P74 AN4 P75 AN5 AV REF AV SS V DD V DD EA P33 SO SB0 P32 SCK P31 T X D P30 R X D P27 SI P26 INTP5 P25 INTP4 ASCK P64 RD P63 A19 P62 A18 P61 A17 P60 A16 RESET X2 X1 V SS V SS P57 A15 P56 A14 P55 A13 P54 A12 P53 A11 P52 A10 P51 A9 27 28 29 30 31 32 33 34 35 3...

Page 37: ...5 INTP4 ASCK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P65 WR P66 WAIT AN6 P67 REFRQ AN7 P07 P06 P05 P04 P03 P02 P01 P00 P37 TO3 P36 TO2 P35 TO1 P34 TO0 P70 AN0 P50 A8 P47 AD7 P46 AD6 P45 AD5 P44 AD4 P43 AD3 P42 AD2 V SS P41 AD1 P40 AD0 ASTB P20 NMI P21 INTP0 P22 INTP1 P23 INTP2 CI P24 INTP3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PD782...

Page 38: ...AD3 P42 AD2 VSS VSS P41 AD1 P40 AD0 ASTB NC P20 NMI P21 INTP0 P22 INTP1 P23 INTP2 CI P24 INTP3 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 P56 A14 P57 A15 V SS V SS X1 X2 RESET NC P60 A16 P61 A17 P62 A18 P63 A19 P64 RD P25 INTP4 ASCK P26 INTP5 P27 SI NC P30 R X D P31 T X D P32 SCK P33 SO SB0 EA V DD V DD AV SS AV REF P75 AN5 P74 AN4 P73 AN3 P72 AN2 P71 AN1 NC 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3...

Page 39: ... Asynchronous serial clock SBO Serial bus SI Serial input SO Serial output NMI Non maskable interrupt INTP0 INTP5 Interrupt from peripherals AD0 AD7 Address data bus A8 A19 Address bus RD Read strobe WR Write strobe WAIT Wait ASTB Address strobe REFRQ Refresh request RESET Reset X1 X2 Crystal EA External access AN0 AN7 Analog input AVREF Reference voltage AVSS Analog ground VDD Power supply VSS Gr...

Page 40: ...ly to VSS through a 10 kΩ resistor G Connect the corresponding pin to VSS Open Leave the corresponding pin unconnected 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A2 A1 A0 VDD VPP A9 P20 NMI Open D0 D1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 A3 A4 A5 A6 A7 CE OE RESET Open G VSS L A14 A13 A12 A11 A10...

Page 41: ...in to VSS Open Leave the corresponding pin unconnected Remark The NC pin is not connected inside the chip 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 L A0 A1 A2 A3 A4 A5 A6 A7 NC CE 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 A9 P20 NMI Open D0 D1 VSS VSS D2 D3 D4 D5 D6 D7 A8 V DD V DD V PP OE RESET Open G V SS V SS A15 A14 A13 A12 A11 A10 L 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ...

Page 42: ...r G Connect the corresponding pin to VSS Open Leave the corresponding pin unconnected 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE RESET Open G VSS A15 A14 A13 A12 A11 A10 L VDD VPP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CE A7 A6 A5 A4 A3 A2 A1 A0 L A8 D7 D6 D5 D4 D3 D2 V SS D1 D0 Open P20 NMI A9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ...

Page 43: ...he corresponding pin unconnected Remark The NC pins are not connected inside the chip CE A7 Open A6 A5 A4 A3 NC A2 A1 A0 NC Open L 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A8 D7 D6 D5 D4 D3 D2 VSS IC D1 D0 Open NC P20 NMI A9 L A10 A11 A12 A13 A14 G V SS V SS G Open RESET NC OE NC V PP V DD V DD NC 19 20 21 22 23 24 25 26 27 28 29 30 31 3...

Page 44: ...pter 1 General 1 VPP Programming power supply RESET Reset D0 D7 Data bus A0 A14 Address bus VSS Ground OE Output enable VDD Power supply CE Chip enable P20 NMI Port 2 non maskable interrupt NC Non connection ...

Page 45: ...otor supply voltage SW input for each mode RESET X1 X2 V SS V DD A8 A15 ASTB AD0 AD7 REFRQ WR RD A16 A19 PD78214 µ Decoder Latch Data bus Address bus Gate array I O expansion Centronics interface etc PROM PD27C256A µ Pseudo SRAM PD24C1000 µ Kanji character generator Print head driver Shift register RS 232C driver Stepping motor Carriage motor Paper feed motor ...

Page 46: ...s bus ALU Data bus Bus interface RAM 256 bytes Note 2 GR Macro service channel Boolean processpr P70 P75 P64 P67 P60 P63 P50 P57 P40 P47 P30 P37 P20 P27 P00 P07 Port RAM Note 3 Temporary registers SP PSW Data bus 8 NMI INTP0 INTP5 R X D T X D ASCK Programmable interrupt controller SCK SO SB0 SI INTP3 TO0 TO1 INTP0 INTP1 INTP2 TO2 TO3 AN0 AN7 P00 P03 P04 P07 AVR EF AV SS INTP5 UART Baud rate genera...

Page 47: ...ory Memory area ROM RAM Special function pins Note 16 bit timer counter consisting of one timer register one capture register and two compare registers Pulse output possible toggle output or PWM PPG output 8 bit timer counter unit 1 consisting of one timer register one capture compare register and one compare register Pulse output possible two four bit real time outputs 8 bit timer counter unit 2 ...

Page 48: ...s and division 16 bits by 8 bits Bit manipulation BCD conversion Others 64 pin plastic shrink DIP 750 mil for all products 64 pin plastic QUIP for all products other than µPD78212 µPD78212 A and µPD78P214 A 68 pin plastic QFJ for all products other than µPD78212 µPD78212 A µPD78213 A and µPD78P214 A 64 pin plastic QFP 14 x 14 mm Note for all products other than µPD78213 A 74 pin plastic QFP 20 x 2...

Page 49: ...sion is being performed as well as the pins selected by the ANI0 to ANI3 bits of the ADM register 64 pin QFP Supported The area at addresses 0FE20H to 0FE7FH can be accessed in any addressing mode 128 bytes Software programmable pull up resistors Not supported Transistor direct drive outputs Not supported PWM PPG output Not supported Scaler for the baud rate generator output Not supported Macro se...

Page 50: ... the macro service mode and other factors and also varies with the sub series For details refer to the table of macro service execution times in the relevant user s manual Restriction imposed on input voltage Restriction imposed on the AVREF voltage A voltage ranging from 0 V to AVREF can be applied only to those pins for which A D conver sion is performed and the pins selected by the ANI0 to ANI3...

Page 51: ...e 74 pin plastic QFPNote 64 pin plastic QUIP 68 pin plastic QFJNote µPD78213 µPD78214 µPD78213 A µPD78214 A Special Product Item Quality grade Package Standard 64 pin plastic shrink DIP 64 pin ceramic shrink DIP with window 64 pin plastic QFP 74 pin plastic QFP 64 pin plastic QUIP 68 pin plastic QFJ µPD78P214 µPD78P214 A Special 64 pin plastic shrink DIP 64 pin plastic QFP No limit Seven days 1 9 ...

Page 52: ...nd µ78P214Note The µPD78P214Note shall be soldered within seven days of its sealed package being opened The µPD78212Note µPD78213Note and µPD78214 can be soldered at any time after their sealed package has been opened None Used only as address data bus AD0 to AD7 Used only as address bus A8 to A15 P64 and P65 are used only as the RD and WR pins respectively 512 bytes at 0FD00H to 0FEFFH Used as bo...

Page 53: ...24 ...

Page 54: ...ut pins Can be collectively connected to internal pull up resistors by means of software Can directly drive LEDs Port 5 P5 Each pin can be assigned to be either an input or output pin Input pins can be collectively connected to internal pull up resistors by means of software Can directly drive LEDs Port 6 P6 Each of pins P64 to P67 can be assigned to be either an input or output pin Input pins P64...

Page 55: ...wire serial I O Serial clock input output SBI three wire serial I O Time multiplexed address data bus external memory connected High order address bus external memory connected High order address when the addresses are expanded external memory connected Read strobe to external memory Write strobe to external memory Wait insertion Latch timing for addresses A0 to A7 when external memory is accessed...

Page 56: ...her port 0 is used as a normal output port or real time output port When the RESET signal is input the output of port 0 becomes high impedance resulting in the contents of the output latches becoming undefined 2 P20 to P27 port 2 Inputs Port 2 is an eight bit input port P22 to P27 are provided with software programmable pull up resistors P20 to P27 also act as input pins for control signals such a...

Page 57: ... INTP1 Capture trigger input for eight bit timer counter unit 2 INTP2 External count clock input for eight bit timer counter unit 2 INTP3 Capture trigger input for 16 bit timer counter INTP5 External trigger input for A D converter iii CI clock input External clock input for eight bit timer counter unit 2 iv ASCK asynchronous serial clock External baud rate clock input v SI serial input Serial dat...

Page 58: ...t with output latches is provided with software programmable pull up resistors and can directly drive LEDs Its pins can be collectively used as input or output pins by specifying the memory expansion mode register MM It acts as a time multiplexed address data bus AD0 to AD7 when external memory or I O devices are expanded In the case of the µPD78213 it acts as a time multiplexed address data bus A...

Page 59: ...being applied P60 to P63 is high impedance When the RESET signal is released the output of these pins is low level Design the peripheral circuit so that it operates normally when pins P60 to P63 initially output low level Remark For details see Chapter 13 a Port mode P60 to P63 are an output port Each of pins P64 to P67 can be used for input or output by specifying the port 6 mode register PM6 acc...

Page 60: ... Mode for the µPD78P214 1 P20 NMI Input Input used for setting the µPD78P214 to PROM programming mode When a voltage of 12 5 V is applied to this pin and the RESET pin goes low the µPD78P214 enters PROM programming mode 2 RESET Input Input used for setting the µPD78P214 to PROM programming mode When a low level signal is applied to this pin and a voltage of 12 5 V is applied to the P20 NMI pin the...

Page 61: ...32 µPD78214 Sub Series 9 VSS Ground 10 NC non connection Not connected inside the chip ...

Page 62: ...Connect to VDD or VSS Connect to VDD Leave open Connect to VDD when used as an input pin Leave open when used as an output pin Connect to VDD when used as an input pin Leave open when used as an output pin Connect to VDD Note when used as an input pin Leave open when used as an output pin Connect to VSS Leave open Connect to VDD or VSS Note Connect to VSS Input Input output Output Input output Inp...

Page 63: ...Type 8 A Data VDD P N IN OUT Output disable VDD P Pull up enable Type 9 Type 10 A Data VDD P N IN OUT Output disable VDD P Pull up enable Type 11 Open drain Schmitt trigger input with hysteresis characteristics Type 5 A Type 2 A IN VDD P Pull up enable Data VDD P N IN OUT Output disable VDD P Pull up enable Input enable Input enable N P IN Vref Threshold voltage Comparator Data VDD P N IN OUT Outp...

Page 64: ...vel Design the peripheral circuit so that it operates satisfactorily when pins P60 to P63 initially output the low level 2 When an I O pin is used as both an input and output pin connect the pin to the VDD pin through a resistor of less than 100 kilohms Especially when the RESET pin goes to a voltage higher than the low level upon power on or when an I O pin is switched with software ...

Page 65: ...36 ...

Page 66: ...sion mode external memory 960K bytes 10000H to FFFFFH is mapped as expanded data memory 2 µPD78213 Programmemoryismappedtoexternalmemory 64768bytes 00000Hto0FCFFH Thisareacanalsobeused as data memory Data memory is mapped to internal RAM 512 bytes 0FD00H to 0FEFFH In 1M byte expansion mode external memory 960K bytes 10000H to FFFFFH is mapped as expanded data memory 3 µPD78214 µPD78P214 Program me...

Page 67: ...data memory Program memory data memory Memory space 1M byte External memoryNote 1 960K bytes Special function registers SFR 256 bytes Note 2 Internal RAM 384 bytes External memory 56704 bytes Internal ROM 8K bytes 0FEC2H 0FEFFH 0FEE0H 0FEDFH 0FD80H 01FFFH 00800H 007FFH 00000H General registers 32 bytes Data area 512 bytes Macro service control words 30 bytes Program area 4K bytes CALLF entry area ...

Page 68: ...a memory Memory space 1M byte External memory Note 1 960K bytes Special function registers SFR 256 bytes Note 2 Internal RAM 384 bytes External memory 64896 bytes 0FEC2H 0FEFFH 0FEE0H 0FEDFH 0FD80H 00800H 007FFH 00000H General registers 32 bytes Data area 512 bytes Macro service control words 30 bytes CALLF entry area 2K bytes Program area 1920 bytes CALLT table area 64 bytes Vector table area 64 ...

Page 69: ...dress Data memory Memory space 1M byte External memoryNote 1 960K bytes Special function registers SFR 256 bytes Note 2 Internal RAM 512 bytes External memory 64768 bytes 0FEC2H 0FEFFH 0FEE0H 0FEDFH 0FD00H 00800H 007FFH 00000H General registers 32 bytes Data area 512 bytes Macro service control words 30 bytes CALLF entry area 2K bytes Program area 1920 bytes CALLT table area 64 bytes Vector table ...

Page 70: ...rogram memory data memory Program memory data memory Memory space 1M byte External memoryNote 1 960K bytes Special function registers SFR 256 bytes Notes 2 3 Internal RAM 512 bytes External memory 48384 bytes Internal ROM 16K bytes 0FEC2H 0FEFFH 0FEE0H 0FEDFH 0FD00H 03FFFH 00800H 007FFH 00000H General registers 32 bytes Data area 512 bytes Macro service control words 30 bytes Program area 12K byte...

Page 71: ...f an interrupt request occurs The low order eight bits of the 16 bit address are stored at even numbered addresses and the high order eight bits at odd numbered addresses Table 3 1 Vector Table Vector table address 00000H 00002H 00006H 00008H 0000AH 0000CH 0000EH 00010H 00012H 00014H 00016H 00018H 0001AH 0001CH 00020H 00022H 00024H 00026H 0003EH Interrupt request Reset RESET input NMI INTP0 INTP1 ...

Page 72: ...area This area allows the µPD78214 in external memoryexpansionmode selectedbymemoryexpansionmoderegisterMM andµPD78213 ROM less toaccess external peripheral I O Caution Never access an address to which no SFR is mapped in this area If this is attempted theµPD78214 may enter a deadlock To restore the device from the deadlock a reset signal must be input 3 1 4 External SFR Area In the SFR area the 1...

Page 73: ... Specifying bank 1 as the main bank and bank 5 as the sub bank and transferring the data from bank 5 to bank 1 MOV MM 47H Selects memory expansion mode MOV PM6 1H Sets the main bank register PM6 MOV P6 5H Sets the sub bank register P6 MOV B 0FFH Sets the loop counter LOOP MOV A HL Reads data from bank 5 The contents of register P6 are added as the most significant address MOV DE A Stores the data ...

Page 74: ...instruction is executed The PSW is restored when an RETI RETB or POP PSW instruction is executed When RESET is input the PSW is set to 02H In this state no interrupt requests can be acknowledged Fig 3 7 Configuration of the Program Status Word IE Z RBS1 AC RBS0 0 ISP CY 7 6 5 4 3 2 1 0 PSW 1 Carry flag CY This flag indicates whether an overflow or underflow occurs when an add subtract instruction ...

Page 75: ...are permitted The ISP flag interrupt mask flag corresponding to each interrupt request and priority designation flag control the acknowledgment of an interrupt request When the EI instruction is executed the IE flag is set 1 When the DI instruction is executed or when an interrupt is acknowledged the flag is reset 0 3 2 3 Stack Pointer SP This 16 bit register holds the first address of a stack are...

Page 76: ...dressing the entire 64K bytes can be accessed A stack area cannot be mapped in the SFR area or internal ROM area 2 The SP becomes undefined when RESET is input Meanwhile nonmaskable interrupts can be acknowledged immediately after a reset is released If a nonmaskable interrupt request occurs while the SP is undefined immediately after a reset is released an unpredictable operation may be carried o...

Page 77: ...ective of whether the area is used for general purpose registers Remark To restore the current register bank after it is changed to a different register bank execute the PUSH PSW instruction to save the PSW to a stack then execute the SEL RBn instruction The POP PSW instruction can restore the register bank if the stack position is not changed If an interrupt handling program changes the register ...

Page 78: ...essing AX RP0 Central register for the transfer of 16 bit data or arithmetic logical operations X R0 Register that can hold bit data B R3 Register with the functions of a loop counter The register can be used by the DBNZ instruction This register can also hold the offset value for indexed addressing C R2 Register with the functions of a loop counter The register can be used by the DBNZ instruction...

Page 79: ...The following column headings are used Symbol Symbol indicating the built in SFR This is a reserved word for NEC s assembler RA78K II For the C compiler CC78K II the pragma sfr instruction allows this symbol to be used as an sfr variable R W Whether the contents of the SFR can be read or written R W Read write R Read only W Write only Bit unit Number of bits that can be manipulated when the SFR is...

Page 80: ...ter Real time output port control register 16 bit compare register 0 16 bit timer counter 16 bit compare register 1 16 bit timer counter 8 bit compare register 8 bit timer counter 1 8 bit compare register 8 bit timer counter 2 8 bit compare register 8 bit timer counter 2 8 bit compare register 8 bit timer counter 3 16 bit capture register 16 bit timer counter 8 bit capture register 8 bit timer cou...

Page 81: ...l register Serial shift register Asynchronous serial interface mode register Asynchronous serial interface status register Serial reception buffer UART Serial transmission shift register UART Baud rate generator control register Standby control register Memory expansion mode register Programmable weight control register Refresh mode register Interrupt request flag register L Interrupt request flag...

Page 82: ...to 0FFFFH If this is attempted the µPD78214 may enter a deadlock To clear the deadlock a reset signal must be input to the device 4 Initializing the stack pointer The SP becomes undefined when RESET is input Meanwhile nonmaskable interrupts can be acknowledged immediately after a reset is released If a nonmaskable interrupt request occurs while the SP is undefined immediately after a reset is rele...

Page 83: ...54 ...

Page 84: ...uency divider divides the output from the clock oscillator fXX for the crystal ceramic oscillation fX for the external clock by two and generates the internal system clock CLK Fig 4 2 External Circuit for the Clock Oscillator a Crystal ceramic oscillation b External clock Caution When using the clock oscillator the adverse influence of stray capacitance must be avoided When configuring the circuit...

Page 85: ...f the inverted signal is not input to the pin X2 malfunctions may readily occur due to noise 3 When inputting an external clock use HCMOS or a device having equivalent drive capability 4 Do not draw signals from pins X1 and X2 Draw signals from point a shown in Fig 4 3 Fig 4 3 Point from Which Signals Can Be Drawn When an External Clock Is Input PD78214 µ X1 X2 a 5 Minimize the length of the line ...

Page 86: ... oscillator as close as possible to pins X1 and X2 2 Do not let other signal lines cross the circuit enclosed in a dashed line Fig 4 5 Incorrect Oscillator Connections a The wiring length of the external circuit is too long b A signal line is allowed to cross the oscillator X2 PD78214 µ X1 VSS X2 PD78214 µ X1 VSS Pnm ...

Page 87: ... crystal requires a few milliseconds and a ceramic resonator several hundreds of microseconds for the oscillation to settle The oscillation settling time is determined as described below Ensure that sufficient time is allowed for the oscillation to settle 1 At power on RESET input reset period 2 At return from STOP mode i RESET input reset period ii PeriodinwhichtheNMIsignalisactive periodspecifie...

Page 88: ... function of each port For ports 2 through 6 software can specify whether to use a built in pull up resistor for inputs Fig 5 1 Port Configuration Port 3 Port 5Note Port 6Note Port 7 Port 4Note Port 0 Port 2 P00 P07 P20 P27 P30 P37 P40 P47 P50 P57 P60 P63 P70 P75 P64 P67 6 4 8 8 8 Note For µPD78213 P40 through P47 P50 through P57 P64 or P65 does not function as ports ...

Page 89: ... Output mode Total In 6 bit units P22 P27 For all input pins at a time In 8 bit units For all input pins at a time For all input pins at a time 14 14 28 10 12 12 54 36 Note For µPD78213 P40 through P47 P50 through P57 P64 or P65 does not function as ports Table 5 2 Number of I O Ports Values enclosed in parentheses apply to the µPD78213 5 2 PORT 0 Port 0 is an 8 bit output only port with an output...

Page 90: ...ve FFH 00H PM0 Cannot be set High impedance state output buffer OFF Output mode output buffer ON Specifies P0n pin mode n 0 to 7 FFH when RESET is input To use port 0 as a real time output port it is necessary to set the P0LM and P0HM bits of the real time output port control register RTPC to 1 When the P0LM and P0HM bits are set the output buffer for each pin is turned on and the contents of the ...

Page 91: ...ied to be a real time output port no data can be written to the output latch However it is possible to read the contents of the output latch if it is in the real time output port mode Fig 5 4 Port Specified as an Output Port 5 2 4 Built In Pull Up Resistor Port 0 has no built in pull up resistor 5 2 5 Driving Transistors Because port 0 has an enhanced driving capacity for the high level side of th...

Page 92: ... each pin can be read and tested b Function as a control signal input pin i NMI nonmaskable interrupt The NMI pin receives a nonmaskable interrupt request from the outside The external interrupt mode register INTM0 specifies which edge rising or falling is valid as an interrupt request signal ii INTP0 through INTP5 interrupt from peripherals The INTP0 through INTP5 pins receive interrupt requests ...

Page 93: ...eceive control signals A register such as a control register in the hardware is used to specify what control signal to receive 5 3 3 Operation Port 2 is an input only port and the level of each pin of it can be read and tested For P20 through P27 the level from which noise has be removed can be read and tested See Chapter 11 for removing noise WRPUO Pull up resistor option register PUO2 RDPUO Inte...

Page 94: ... of the pull up resistor option register PUO can specify whether to use the built in pull up resistors at P22 through P27 for all six pins at one time It is impossible to specify use of the built in pull up resistor for an individual bit independently of the other bits P20 or P21 does not have a built in pull up resistor Fig 5 8 Built In Pull Up Resistor Format 0 7 PUO6 6 PUO5 5 PUO4 4 PUO3 3 PUO2...

Page 95: ...t of this port in either the input or output mode separately from the other bits Each pin has a software programmable built in pull up resistor In addition to I O functions each pin works as control signal pin The port 3 mode control register PMC3 can specify the mode of operation for each pin separately from the other pins as listed in Table 5 4 The level of any pin can be read and tested regardl...

Page 96: ... control pin independently of the other pins as described below i RxD receive data The RxD pin receives serial data from the asynchronous serial interface ii TxD transmit data The TxD pin outputs serial data to the asynchronous serial interface iii SCK serial clock The SCK pin is a serial clock I O pin for the clock synchronized serial interface iv SO serial output SB0 serial bus The SO pin output...

Page 97: ...n Fig 5 10 through 5 13 show the configuration of port 3 Fig 5 10 Block Diagram of P30 Port 3 P30 Internal bus WRPM30 Port 3 mode register PM30 WRPMC30 PMC30 WRP30 P30 RDPUO WRPUO RDPMC30 RDP30 RDP30 RxD input PUO3 Pull up resistor option register VDD ...

Page 98: ...lock Diagram of P31 and P34 through P37 Port 3 Internal bus RDPUO WRPUO WRPM3n Port 3 mode register PM3n WRPMC3n PMC3n WRP3n P3n RDPMC3n RDP3n Pull up resistor option register PUO3 P3n n 1 4 5 6 7 VDD TO TxD output RDP3n Selector Output latch ...

Page 99: ... Block Diagram of P32 Port 3 Internal bus RDP32 P32 RDPUO WRPUO Pull up resistor option register PUO3 WRPM32 Port 3 mode register PM32 WRPMC32 PMC32 RDPMC32 WRP32 P32 Selector RDP32 SCK output External SCK VDD SCK input Output latch ...

Page 100: ...data transfer instruction it cannot be bit manipulated or read accessed In addition to I O port functions each pin of port 3 works as a control signal pin As shown in Fig 5 15 the port 3 mode control register PMC3 can specify the mode of control for each pin Internal bus RDOUT P33 VDD RDIN RDPUO WRPUO Pull up resistor option register PUO3 WRPM33 Port 3 mode register PM33 WRPMC33 PMC33 RDPMC33 WRP3...

Page 101: ...ut 0 1 PMC37 7 PMC36 6 PMC35 5 PMC34 4 PMC33 3 PMC32 2 PMC31 1 PMC30 0 PMC3 PMC30 RxD input mode I O port mode Specifies control mode of pin P30 00H when RESET is input 0 1 PMC31 TxD output mode I O port mode Specifies control mode of pin P31 0 1 PMC32 SCK I O mode I O port mode Specifies control mode of pin P32 0 1 PMC33 SO output mode SB0 I O mode I O port mode Specifies control mode of pin P33 ...

Page 102: ...ing to the pins in the input mode or the control mode become undefined except for the bits manipulated by the SET1 or CLR1 instruction Special care should be taken if bits are switched between the input and output modes The same holds true when the port is manipulated using 8 bit arithmetic logical instructions 2 Input port The level of each pin of port 3 can be transferred to the accumulator by a...

Page 103: ...nal pin 5 4 4 Built In Pull Up Resistor Port 3 has built in pull up resistors When port 3 must be pulled up the built in pull up resistors should be used Use of the built in pull up resistors can reduce the number of the required components and the required installation space Use of a built in pull up resistor can be specified for each bit of port 3 independently of the other bits by the PUO3 bit ...

Page 104: ...ble built in pull up resistor and can drive an LED directly When an external memory or I O device is expanded port 4 functions as a time division address data bus AD0 through AD7 For the µPD78213 port 4 functions only as a time division address data bus AD0 through AD7 When the RESET signal is input port 4 becomes an input port high output impedance and the contents of the output latch become unde...

Page 105: ...perating mode of port 4 as listed in Table 5 5 Table 5 5 Port 4 Operating Modes 1 1 1 0 0 0 1 MM2 0 0 1 MM1 0 1 1 MM0 EA pin MM register bit Operation mode Input port Output port Address data bus AD0 AD7 For the µPD78213 port 4 functions only as the address data bus AD0 through AD7 Internal data bus WRPUO Pull up resistor option register PUO4 WRP4n RDP4n RDPUO Output latch P4n n 0 to 7 VDD MM0 MM2...

Page 106: ...instruction or other similar instruction regardless of the current mode of the port operation If a pin is specified as an input port however the latched data is not output to the port pin because the output buffer at the pin is in the high impedance state When the pin is switched to the output mode the contents of the output latch are output to the port pin If a pin is specified as an input port t...

Page 107: ...ther by the PUO4 bit of the pull up resistor option register PUO Use of built in pull up resistors can be specified for this port regardless of the current mode input or output of the port Fig 5 24 Pull Up Resistor Option Register Format Caution For the µPD78213 port 4 is used as an address data bus Therefore the PUO4 bit must be kept to be 0 and a built in pull up resistor must not be connected F...

Page 108: ...owlevelsideoftheoutputbufferhasanenhanceddrivingcapacitysothatitcandriveanLEDdirectly on an active low signal Fig 5 26 is an example of such an output buffer Fig 5 26 Example of Driving an LED Directly PD78214 µ VDD P4n n 0 to 7 Internal bus VDD P40 P41 P42 P46 P47 Input buffer Pull up resistor option register PUO PUO4 ...

Page 109: ... contents of the output latch become undefined 5 6 1 Hardware Configuration Fig 5 27 shows the hardware configuration of port 5 Fig 5 27 Block Diagram of Port 5 5 6 2 Setting the I O Mode and Control Mode The port 5 mode register PM5 can put each pin of port 5 in either the input or output mode independently of the other pins as shown in Fig 5 28 The PM5 register is loaded with data using an 8 bit...

Page 110: ... instruction Fig 5 29 Port Specified as an Output Port 2 Input port The level of each pin of port 5 can be transferred to the accumulator by a transfer instruction Also in this case data can be written to the output latches and all output latches store data transferred from the accumulator by a transfer instruction or other similar instruction regardless of the current mode of the port operation I...

Page 111: ...t be pulled up the built in pull up resistors should be used Use of the built in pull up resistors can reduce the number of the required components and the required installation space Use of a built in pull up resistor can be specified for each pin of port 5 independently of the other pins by the PUO5 bit of pull up resistor option register PUO and the port 5 mode register PM5 When the PUO5 bit is...

Page 112: ...thelowlevelsideoftheoutputbufferhasanenhanceddrivingcapacitysothatitcandriveanLEDdirectly on an active low signal Fig 5 33 is an example of such an output buffer Fig 5 33 Example of Driving an LED Directly PD78214 µ VDD P5n n 0 to 7 Internal bus VDD P50 P51 P52 P56 P57 Input buffer PUO5 PUO Port 5 mode register PM5 ...

Page 113: ...he RESET signal exists P60 through P63 are kept in the high impedance state When the RESET signal disappears they output a low level So it is necessary to design the external circuit so that P60 through P63 are allowed to output a low level during the initial state Remark See Chapter 13 for details a Port mode P60 through P63 are output only circuits Each of P64 through P67 can be specified to be ...

Page 114: ...Configuration Fig 5 34 through 5 37 show the hardware configuration of port 6 Fig 5 34 Block Diagram of P60 through P63 Port 6 P6n n 0 1 2 3 WRMM6 Memory expansion mode register MM6 RDMM6 WRP6 Output latch P6n WRPM6 Port 6 mode register PM6n RDP6 Memory reference instruction without Memory reference instruction with Internal bus ...

Page 115: ...agram of P64 and P65 Port 6 Internal bus P64 P65 VDD RDIN Selector RDPUO WRPUO Pull up resistor option register PUO6 Port 6 mode register P64 P65 WRPM64 PM65 Output latch PM64 PM65 WRP64 P65 EA External extended mode RD signal WR signal RDOUT ...

Page 116: ...5 Fig 5 36 Block Diagram of P66 Port 6 Internal bus P66 VDD RDIN RDPUO WRPUO Pull up resistor option register PUO6 Port 6 mode register PM66 WRPM66 Output latch WRP66 RDOUT External wait specification P66 Wait input A D converter ...

Page 117: ...n only as output pins for RD and WR respectively Table 5 8 Port 6 Control Pin Functions and the Required Operations P60 P61 P62 P63 P64 P65 P66 P67 Pin I O Function A16 A17 A18 A19 RD WR WAIT REFRQ Operation needed to make port 6 function as control pins Output Output Output Output Output Output Input Output Set the MM6 bit of the MM register to 1 For the µPD78213 no special operation is needed Fo...

Page 118: ...out When the 1M byte expansion function is not used reset PM63 through PM60 to all 0s Caution To use analog inputs AN6 and AN7 put PM66 and PM67 in the input mode Remark The lower four bits P60 through P63 of port 6 are an output only port PM67 7 PM66 6 PM65 5 PM64 4 PM63 3 PM62 2 PM61 1 PM60 0 PM6 PM63 PM62 PM61 PM60 Memory bank specificationNote F H when RESET is input 0 0 0 0 0 0 0 1 Bank 0 Ban...

Page 119: ...eration If a pin is specified as an input port however the latched data is not output to the port pin because the output buffer at the pin is in the high impedance state When the bit is switched from the input mode to the output mode the contents of the output latch are output to the corresponding port pin If a bit is specified as an input port the contents of the output latch for the bit cannot b...

Page 120: ...the PUO6 bit of pull up resistor option register PUO and the port 6 mode register PM6 When the PUO6 bit is 1 the built in pull up resistor for a pin specified by the PM6 PM6n 1 n 4 to 7 is connected P60 through P63 do not have a built in pull up resistor Fig 5 41 Pull Up Resistor Option Register Format Remark Resetting the PUO to 00H can reduce the required current in the STOP mode Caution To use ...

Page 121: ...analog input pins AN0 through AN5 as well as input port pins The level of each pin of port 7 can be read and tested although it is a dual function pin 5 8 1 Hardware Configuration Fig 5 43 shows the hardware configuration of port 7 Fig 5 43 Block Diagram of Port 7 Internal bus RDIN P7n n 0 to 5 Analog input 5 8 2 Setting the I O Mode and Control Mode Port 7 is an input only port Port 7 is designed...

Page 122: ...when the RESET signal is being supplied take an appropriate action using an external circuit 2 Some operations of the pull up resistor option register PUO which is used to specify connection of built in pull up resistors cannot be emulated by an in circuit emulator because of the following restrictions The contents of the PUO register cannot be read correctly Bit manipulation instructions or logic...

Page 123: ...n of built in pull up resistors for port 6 10 When P66 and P67 are used as analog input pins AN6 and AN7 respectively or when A D conversion is not performed do not apply a voltage out of the range AVSS through AVREF to these pins if AN6 and AN7 are selected for ANI0 through ANI2 of the A D converter mode register ADM See Chapter 8 for details 11 To use the P66 WAIT pin as the WAIT pin it is neces...

Page 124: ...ut to the outside simultaneously when a timer interrupt or external interrupt occurs The term real time output port refers to a pin used to output such data to the outside The real time output function handles the following two types of real time output data 4 bits 2 channels 8 bits 1 channel Combined use of the real time output function and the macro service function described later implements a ...

Page 125: ...put Port 4 4 4 P00 P01 P02 P03 P04 P05 P06 P07 INTP0 P0ML INTC10 Selector Selector P0MH P0ML EXTR P0MH BYTE INTC11 4 P0L P0H Buffer register 8 Output latch P0 4 bit real time output P0H 4 bit real time output P0L 8 bit real time output P0 BYTE Internal bus RTPC EXTR ...

Page 126: ...mapped to independent addresses in the SFR area as shown in Fig 6 3 When the 4 bit 2 channel real time output function is specified data can be set in each buffer register P0H or P0L independently When the 8 bit 1 channel real time output function is specified 8 bit data can be set in the buffer registers by writing to either one P0H or P0L Table 6 1 lists the operating modes of port 0 and the ope...

Page 127: ...Output latch Buffer registerNote Buffer registerNote Output latch Buffer register Buffer register Buffer register Buffer register Buffer register Buffer register Output latch Buffer register Buffer register Output latch Buffer register Buffer register Note The contents of the P0H are read to the high order 4 bits and the contents of the P0L are read to the low order 4 bits Remark The output latche...

Page 128: ...can output data at each pin of port 0 sequentially at arbitrary intervals see Section 12 4 If external interrupt INTP0 is selected as an external output trigger source data can be output from port 0 in synchronization with an external event Table 6 2 Output Trigger for the Real Time Output Port When P0MH P0ML 1 0 1 0 1 Output mode RTPC register BYTE EXTR 0 1 8 bit real time output 4 bit real time ...

Page 129: ... D00 D01 D03 D04 0H CR11 CR11 CR11 CR11 FFH Timer starts INTC11 interrupt request CPU operation Buffer register P0H Output latches P07 P04 8 bit timer counter 1 The contents of the buffer register and compare register are rewritten by software processing or macro service see Section 12 4 ...

Page 130: ...INTC11 interrupt request INTC10 interrupt request CPU operation D01 D11 D00 D01 D02 D03 D04 D03 D02 D12 D13 D12 D13 D10 D11 D14 CR11 CR10 CR11 CR11 CR11 CR10 CR10 FFH Buffer register P0H Buffer register P0L Output latches P07 P04 Output latches P03 P00 The contents of the buffer register and compare register are rewritten by software processing or macro service see Section 12 4 ...

Page 131: ... data to be set in the control register Fig 6 8 illustrates the procedure to set the data and Fig 6 9 is a flowchart of the interrupt handling routine Fig 6 6 Real Time Output Port Operation Timing 8 bit timer counter 1 0H INTC10 interrupt request CR10 CR10 CR10 CR10 FFH D01 D02 D03 D04 D00 D01 D02 D03 D03 D02 D01 D00 Hi z Buffer register P0L Output latches P00 P03 Output latches P00 P03 Change th...

Page 132: ... INTP0 from the buffer register to the output latch Uses pins P04 to P07 as ordinary output ports Selects a 4 bit separate real time output port Fig 6 8 Real Time Output Function Setting Procedure INTC10 interrupt Real time output port Set an initial value in the P0 output latch Set the value to be output next in the P0L buffer register Set the real time output port control register Set the 8 bit ...

Page 133: ...nts Use of any of these methods does not allow use of the compare register CR10 for 8 bit timer counter 1 a Do not use 8 bit timer counter 1 b When using the capture compare register CR11 for 8 bit timer counter 1 as the compare register use the compare register as an interval timer in a mode in which clearing occurs when the contents of the capture compare register CR11 coincide with the contents...

Page 134: ... it is specified that data transfer from the buffer register to the output latch be performed according to a signal from the INTP0 pin data transfer may occur according to an erroneously detected edge Keep in mind this characteristic when using the in circuit emulator See the notes in Chapter 11 for details of erroneous detection of edges ...

Page 135: ...106 ...

Page 136: ...r counter 2 ch 2 ch 2 2 ch 2 2 ch 2 ch 2 1 ch 1 8 bit timer counter 1 8 bit timer counter 2 8 bit timer counter 3 Interval timer External event counter One shot timer Timer output Toggle output PWM PPG output Real time output Pulse width measurement Number of interrupt requests Serial interface clock source Functions Types Thesetimer counterunitscanbeusedasa7 channeltimerbecauseseveninterruptreque...

Page 137: ... register CR11 INTP0 Edge detector INTP0 Prescaler INTC10 INTC11 To the real time output port 8 bit timer counter unit 2 fCLK 16 Timer register TM2 Compare register CR20 OVF Prescaler INTP2 CI Edge detector INTP2 INTP1 Edge detector INTP1 Pulse output control TO2 TO3 INTC20 INTC21 Event input Compare register CR21 Capture register CR22 8 bit timer counter unit 3 fCLK 8 Timer register TM3 Compare r...

Page 138: ... 6 MHz 2 Programmable square wave output The 16 bit timer counter outputs a square wave separately on the TO0 pin and TO1 pin Table 7 3 Programmable Square Wave Output Setting Range of 16 Bit Timer Counter Minimum pulse width 8 fCLK 1 3 µs Maximum pulse width 216 8 fCLK 87 4 ms The values in parentheses are based on fCLK 6 MHz 3 Pulse width measurement The 16 bit timer counter measures the pulse w...

Page 139: ...1 INTC00 Output con trol circuit Output con trol circuit RESET MOD1 MOD0 PWM PPG output control Coincidence 1 8 ES30 16 16 Clear 16 16 16 16 f CLK 8 INTP3 Overflow Capture register CR02 Capture trigger 16 bit timer 0 TM0 ES31 Mode register INTM1 P24 INTP3 Compare register CR00 Coincidence Capture compare control register CRC0 OVF0 CE0 8 Timer control register TMC0 Internal bus Edge detector 16 ...

Page 140: ...ation using a 16 bit manipulation instruction When the RESET signal is applied the CR02 register becomes undefined 4 Edge detector The edge detector detects a valid edge of an external input signal When the edge detector detects on the INTP3 input pin a valid edge specified in external interrupt mode register 1 INTM1 INTP3 and a capture trigger are generated See Fig 11 2 for information about the ...

Page 141: ... value of the CR01 compare register and the count value of TM0 The CRC0 register is also used to specify a timer output TO0 TO1 mode The CRC0 register allows only write operation using an 8 bit manipulation instruction Fig 7 4 shows the format of the CRC0 register When the RESET signal is applied the CRC0 register is cleared to 10H Fig 7 4 Format of Capture Compare Control Register 0 CRC0 7 6 5 4 ...

Page 142: ...ter When the RESET signal is applied the TOC register is cleared to 00H Fig 7 5 Format of Timer Output Control Register TOC 7 6 5 4 3 2 1 0 TOC ENTO3 ALV3 ENTO2 ALV2 ENTO1 ENTO0 ALV1 ALV0 ALV0 ALV1 ENTO1 0 0 0 1 1 1 Active level for TO0 pin When toggle output is specified When toggle output is specified When PWM PPG output is specified Low level High level Low level High level Active level for pin...

Page 143: ... then capture operation and coincide with signal generation stop If the CE0 bit is set to 1 when the CE0 bit is already set to 1 TM0 is not cleared but continues count operation If the count clock is applied when the value of TM0 is FFFFH TM0 is set to 0000H At this time OVF0 is set to send the overflow signal to the output control circuit OVF0 can be cleared only by software Count operation conti...

Page 144: ...red by a Coincidence with Compare Register CR01 Count clock Compare register CR01 TM0 n 1 n 0 1 Coincidence between TM0 and CR01 Cleared here n TM0 can also be cleared by software when the CE0 bit of the timer control register TMC0 is reset to 0 Similarly clear operation is performed by the count clock pulse following the resetting of CE0 bit to 0 If the CE0 bit is set to 1 before TM0 is reset to ...

Page 145: ...ed Count clock TM0 CE0 n 1 n 0 0 1 When the CE0 bit is set to 1 after this count clock counting starts from 0 on the count clock input after the CE0 bit has been set c Restart before 0 is set in TM0 cleared Count clock TM0 CE0 n 1 When the CE0 bit is set to 1 before this count clock Clearing TM0 by CE0 0 and counting by CE0 1 are performed simultaneously n 0 1 2 ...

Page 146: ...generated After the value of the CR01 register coincides with a count value of TM0 the count value of TM0 can be cleared Thus the 16 bit timer counter can operate as an interval timer for repeatedly counting up to the value set in the CR01 register Caution Before the 16 bit timer counter can perform a compare operation a value must be loaded into the compare register or registers used Fig 7 9 Comp...

Page 147: ... operation is loaded and held in the CR02 capture register Until the next capture trigger occurs the value of the CR02 register is held A valid edge used as a capture trigger is set using external interrupt mode register 1 INTM1 When both a rising edge and falling edge are set as capture triggers the pulse width of an applied external signal can be measured When a capture trigger is generated usin...

Page 148: ...pture value must be used after checking by software to see if the INTP3 interrupt was generated normally or generated on an erroneously detected edge For detailed information about erroneous edge detection see Section 11 4 7 1 6 Basic Operation of Output Control Circuit The output control circuit controls the levels of the timer outputs TO0 TO1 according to the overflow signal or the coincidence s...

Page 149: ...ied high low PWM output high low active PWM output high low active Tied high low Toggle output low high active Toggle output low high active Tied high low Toggle output low high active Tied high low Toggle output low high active PWM output high low active Tied high low PWM output high low active PWM output high low active Tied high low PWM output high low active PPG output high low active Tied hig...

Page 150: ...peration mode where the level of output is inverted each time the value of a compare register CR00 CR01 coincides with the value of 16 bit timer 0 TM0 The output level of TO0 is inverted when the value of CR00 coincides with the value of TM0 The output level of TO1 is inverted when the value of CR01 coincides with the value of TM0 Fig 7 12 Toggle Output Operation Table 7 6 TO0 and TO1 Toggle Outpu...

Page 151: ...d value set in compare register 8 2 65536 8 value set in compare register 65536 Caution In PWM output the actual pulse width is longer than a value obtained with the approximate expression by two clock pulses of fCLK for the active level and is shorter than such an approximate value by two clock pulses of fCLK for the inactive level Take this point into consideration when high precision output is ...

Page 152: ...g 7 15 PWM Output When CR00 FFFFH Remark ALV0 0 FFFFH INTO00 FFFFH FFFFH FFFFH FFFFH TO0 TM0 count value Count clock period T OVF flag Duty factor 100 99 998 0 1 2 0 1 2 0 Pulse width Pulse period 65536T 65535 65536 T FFFFH FFFFH CR00 FFFFH CR00 CR00 CR01 CR01 TM0 count value 0H INTC00 INTC01 TO0 TO1 ...

Page 153: ...e though CR00 coincides with TM0 Cautions 1 If a value less than the value of 16 bit timer 0 TM0 is set in a compare register CR00 CR01 a PWM signal with a 100 duty factor is output Rewrite the CR00 or CR01 compare register if required by using an interrupt generated by a coincidence between TM0 and the compare register Fig 7 17 Example of PWM Output Signal with a 100 Duty Factor TO0 FFFFH CR00 0H...

Page 154: ... CR00 8 fCLK where CR00 CR01 Duty factor PPG pulse width PPG period value set in CR00 8 2 value set in CR01 1 8 value set in CR00 value set in CR01 1 Caution In PPG output the actual pulse width is longer than a value obtained with the approximate expression by two clock pulses of fCLK for the active level and is shorter than such an approximate value by two clock pulses of fCLK for the inactive l...

Page 155: ...0 CR01 Fig 7 20 PPG Output When CR00 0000H Remark ALV0 0 1 2 n n n INTC00 INTC01 TO0 TM0 count value n 1 0 n 1 2 1 0 0 Count period T Pulse period n 1 T Pulse width nT T 1 2 n n n INTC00 INTC01 TO0 TM0 count value 0 Pulse period n 1 T Pulse width 2 fCLK ...

Page 156: ...s with TM0 CR01 Remark ALV0 1 Cautions 1 If a value less than the value of 16 bit timer 0 TM0 is written into the CR00 compare register before the value of CR00 coincides with the value of TM0 a PPG signal with a 100 duty factor is output in that period Rewrite CR00 if required by using an interrupt generated by a coincidence between TM0 and CR00 Fig 7 22 Example of PPG Output Signal with a 100 Du...

Page 157: ...and normal PPG output is resumed Rewrite CR01 if required by using an interrupt generated by a coincidence between TM0 and CR01 Fig 7 23 Example of PPG Output Period Made Longer n3 n1 n2 n4 n2 0H CR00 CR01 TO0 n1 n3 n1 n4 n2 n1 Full count value n3 n5 TM0 The PPG period is extended when a value n2 less than TM0 value n5 is written to CR01 here TO0 becomes inactive when CR00 coincides with TM0 other...

Page 158: ...stem clock fCLK 6 MHz In addition 16 bit timer 0 TM0 has two compare registers so that interval timers with two types of periods can be produced Fig 7 25 shows the setting of control registers Fig 7 26 shows the setting procedure Fig 7 27 shows interrupt handling Fig 7 24 Timing of Interval Timer Operation 1 n n 0H TM0 count value MOD 2n MOD 3n FFFFH FFFFH MOD 2n MOD 3n MOD 4n Timer starts Compare...

Page 159: ...5 4 3 2 1 0 0 0 0 0 0 0 0 1 CRC0 Disables clearing TM0 Both TO0 and TO1 are used for toggle output Fig 7 26 Setting Procedure for Interval Timer Operation 1 Interval timer 1 Set count value in CR00 register Set CRC0 register Start counting Sets bit 3 of TMC0 to 1 INTC00 interrupt CR0 1 CRC0 10H CR00 n 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 TMC0 Overflow flag Enables counting TM0 ...

Page 160: ...s and can count up from 1 3 µs to 87 4 ms at internal system clock fCLK 6 MHz Fig 7 29 shows the setting of control registers and Fig 7 30 shows the setting procedure Fig 7 28 Timing of Interval Timer Operation 2 Remark Interval n 1 8 fCLK 0 n FFFFH INTC00 interrupt Other interrupt program CR00 CR00 n RETI Calculation of timer value at which next interrupt is to occur 0H TM0 count value n Compare ...

Page 161: ... fCLK 6 MHz or more for both the high level and the low level If the pulse width is less than this value no valid edge can be detected thus resulting in a failure to perform capture operation This pulse width measurement allows a pulse width of 2 6 µs to 87 4 ms to be measured with a resolution of 1 3 µs at fCLK 6 MHz As shown in Fig 7 31 the value of 16 bit timer 0 TM0 in count operation is loade...

Page 162: ...ntrol register 0 CRC0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 CRC0 Disables clearing TM0 Both TO0 and TO1 are used for toggle output OVF0 CR02 TM0 count value 0H D0 D1 Captured Captured D1 D0 8 fCLK Captured Count starts CE0 1 D0 D1 D2 D3 D3 D2 8 fCLK 10000H D1 D2 8 fCLK FFFFH FFFFH INTP3 external input signal INTP3 interrupt request Cleared by software Captured D2 D3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 TMC0 Ov...

Page 163: ...gister and MK0L register CRC0 10H X0 0 CE0 1 Initialize buffer memory for capture value Start counting Sets bit 3 of TMC0 to 1 Enable interrupt INTP3 interrupt Specifies valid edge of INTP3 input to be both edges and unmasks interrupt INTP3 interrupt Calculation of pulse width Store captured value in memory Xn 1 CR02 RETI Yn CR02 Xn 7 0 INTM1 0 1 1 6 5 4 3 2 1 0 Specifies valid edge of INTP3 input...

Page 164: ...re for changing the duty factor of PWM output Fig 7 35 Example of PWM Signal Output by 16 Bit Timer Counter FFFFH FFFFH FFFFH CR00 CR00 CR00 Timer starts 0H TM0 count value active low TO0 Fig 7 36 Setting of Control Registers for PWM Output Operation a Timer control register 0 TMC0 b Capture compare control register 0 CRC0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 1 CRC0 Disables clearing TM0 Both TO0 and TO1...

Page 165: ...quest flag Clears bit 4 of IF0L Enable INTC00 interrupt Clears bit 4 of MK0L INTC00 interrupt Duty factor changing processing Set duty factor in CR00 CMK00 0 Disable INTC00 interrupt Sets bit 4 of MK0L CMK00 1 RETI PWM output Set CRC0 register Set TOC register Set P34 pin in control mode Set initial value in compare register Start counting Sets bit 3 of TMC0 CRC0 90H PMC3 4 1 CE0 1 ...

Page 166: ...Timer Counter CR00 CR00 CR00 Timer starts 0H TM2 count value active low TO0 CR01 CR01 CR01 Fig 7 40 Setting of Control Registers for PPG Output Operation a Timer control register 0 TMC0 b Capture compare control register 0 CRC0 c Timer output control register TOC d Port 3 mode control register PMC3 7 6 5 4 3 2 1 0 1 0 0 0 0 1 CRC0 1 1 Clears when TM0 coincides with CR01 TO0 is used for PPG output ...

Page 167: ...H PMC3 4 1 Set duty factor in compare register CR00 Start counting CE0 1 Fig 7 42 Changing Duty Factor of PPG Output CIF00 0 Preprocessing for changing duty factor Clear INTC00 interrupt request flag Clears bit 4 of IF0L Enable INTC00 interrupt Clears bit 4 of MK0L INTC00 interrupt Duty factor changing processing Set duty factor in CR00 CMK00 0 Disable INTC00 interrupt Sets bit 4 of MK0L CMK00 1 R...

Page 168: ...imum interval 28 16 fCLK 683 µs 28 32 fCLK 1 37 ms 28 64 fCLK 2 73 ms 28 128 fCLK 5 46 ms 28 256 fCLK 10 9 ms 28 512 fCLK 21 8 ms Minimum interval 16 fCLK 2 6 µs 32 fCLK 5 3 µs 64 fCLK 10 7 µs 128 fCLK 21 3 µs 256 fCLK 42 7 µs 512 fCLK 85 3 µs The values in parentheses are based on fCLK 6 MHz 2 Pulse width measurement Eight bit timer counter 1 measures the pulse width of a signal applied to the ex...

Page 169: ...eries 7 2 2 Configuration Eight bit timer counter 1 consists of one 8 bit timer 1 TM1 one 8 bit compare register CR10 and one 8 bit capture compare register CR11 Fig 7 43 shows the block diagram of 8 bit timer counter 1 ...

Page 170: ...CE1 OVF1 8 Internal bus Overflow RESET 8 CRC1 CLR11 CM CLR10 RESET INTC10 INTC11 Real time output port Capture compare control register Compare register CR10 8 bit timer 1 TM1 Capture compare register CR11 Caapture trigger ES00 INTM0 INTP0 MPX External interrupt mode register 0 Edge detector 1 8 f CLK 512 Prescaler mode register PRM1 f CLK 256 f CLK 128 f CLK 64 f CLK 32 f CLK 16 ...

Page 171: ...en CR11 is set as a compare register The CR11 register functions as an 8 bit register for holding a value that determines the period of interval timer operation When the value of the CR11 register coincides with the value of TM1 an interrupt request INTC11 is generated In addition this coincide with signal functions also as a real time output port trigger signal Count value clear operation can als...

Page 172: ...1 0 CE2 OVF2 CMD2 0 CE1 OVF1 0 0 TMC1 OVF1 0 1 1 0 CE1 TM1 overflow flag Overflow does not occur Overflow occurs countiing up from FFH to 00H TM1 counting control Clears and stops counting Enables counting These bits control counting for 8 bit timer counter 2 TM2 see Fig 7 67 Remark The OVF1 bit can be reset only by software 2 Prescaler mode register 1 PRM1 The PRM1 register is an 8 bit register u...

Page 173: ... operation of the CR11 capture compare register and the condition for enabling the clear operation of 8 bit timer 1 TM1 The CRC1 register allows only write operation using an 8 bit manipulation instruction Fig 7 46 shows the format of the CRC1 register When the RESET signal is applied the CRC1 register is cleared to 00H Fig 7 46 Format of Capture Compare Control Register 1 CRC1 7 6 5 4 3 2 1 0 CRC...

Page 174: ... then count up operation starts When the CE1 bit is reset to 0 TM1 is cleared to 00H by the next count clock pulse then capture operation and coincide with signal generation stop If the CE1 bit is set to 1 when the CE1 bit is already set to 1 TM1 is not cleared but continues count operation If the count clock signal is applied when the value of TM1 is FFH TM1 is set to 00H At this time OVF1 is set...

Page 175: ...mer 1 TM1 can be automatically cleared If a TM1 clear cause occurs TM1 is cleared to 00H by the next count clock pulse This means that even if a TM1 clear cause occurs TM1 holds the value existing at that time until the next count clock pulse is applied Fig 7 48 TM1 Cleared by a Coincidence with Compare Register CR1m Count clock Compare register CR1m m 0 1 TM1 n 1 n 0 1 Coincidence between TM1 and...

Page 176: ...e count clock pulse following the resetting of CE1 bit to 0 If the CE1 bit is set to 1 before TM1 is reset to 0 by the resetting of the CE1 bit to 0 that is before the first count clock pulse is applied after the CE1 bit is reset to 0 two operations are simultaneously performed one operation is an operation to clear TM1 to 0 and the other operation is a count operation starting with the counting o...

Page 177: ...Compare operation Eight bit timer counter 1 performs an operation to compare the values set in the compare registers with timer count values When the value set in the compare register CR10 and the value set in the capture compare register CR11 specifiedtoperformcompareoperationcoincidewithcountvaluesof8 bittimer1 TM1 theinterruptrequest signals INTC10 for the CR10 register and INTC11 for the CR11 ...

Page 178: ...til the next capture trigger occurs the value of the CR11 register is held A valid edge used as a capture trigger is set using external interrupt mode register 0 INTM0 When both a rising edge and falling edge are set as capture triggers the pulse width of an applied external signal can be measured When a capture trigger is generated using one edge the period of an input pulse signal can be measure...

Page 179: ... Series Fig 7 53 Capture Operation Remark Dn TM1 count value n 0 1 2 CLR10 0 CLR11 0 CM 1 Count starts TM1 count value D0 D1 D2 D2 D1 FFH 0H INTP0 pin input INTP0 interrupt request Capture compare register CR11 OVF1 D0 ...

Page 180: ...8 bit timer counter 1 can be used as an interval timer whose period is as long as the added value See Fig 7 55 In addition 8 bit timer 1 TM1 has two compare registers so that interval timers with two types of periods can be produced Fig 7 56 shows the setting of control registers Fig 7 57 shows the setting procedure Fig 7 58 shows interrupt handling N3 N2 N4 N5 N1 0H TM1 count value Captured Captu...

Page 181: ... 16 32 64 128 256 512 Fig 7 56 Setting of Control Registers for Interval Timer Operation 1 a Timer control register 1 TMC1 b Prescaler mode register 1 PRM1 c Capture compare control register 1 CRC1 7 6 5 4 3 2 1 0 0 0 0 0 0 CRC1 Disables clearing TM1 when CR10 coincides with TM1 Specifies the CR11 register as a compare register Disables clearing TM1 when CR11 coincides with TM1 0 0 0 7 6 5 4 3 2 1...

Page 182: ...nerates an interrupt at intervals of a count time specified beforehand See Fig 7 59 Fig 7 60 shows the setting of control registers and Fig 7 61 shows the setting procedure Interval timer 1 Set count value in CR10 register Set CRC1 register Start counting Sets bit 3 of TMC1 to 1 INTC10 interrupt CE1 1 CRC1 00H CR10 n Set PRM1 register INTC10 interrupt Other interrupt program CR10 CR10 n RETI Calcu...

Page 183: ...7 6 5 4 3 2 1 0 0 0 0 0 1 CRC1 Disables clearing TM1 when CR10 coincides with TM1 Specifies the CR11 register as a compare register Enables clearing TM1 when CR11 coincides with TM1 0 0 0 0H TM1 count value n Compare register CR11 INTC11 interrupt request Interrupt accepted Interval time Interval time Interrupt accepted Cleared Cleared n n Coincidence Coincidence Count starts 7 6 5 4 3 2 1 0 0 0 0...

Page 184: ... 7 62 thevalueof8 bittimer1 TM1 incountoperationisloadedandheldintheCR11capture compare register specified as a capture register on a valid edge either a rising edge or falling edge of a signal applied to the INTP0 pin The pulse width of the input signal is found by multiplying the count clock X fCLK X 16 32 64 128 256 512 by the difference between the TM1 count value Dn loaded and held in the CR1...

Page 185: ...mark Dn TM1 count value n 0 1 2 X 16 32 64 128 256 512 OVF1 Capture compare register CR11 TM1 count value 0H Captured Captured D1 D0 X fCLK Captured Count starts D0 D1 D2 D3 D3 D2 X fCLK 100H D1 D2 X fCLK D3 FFH FFH INTP0 external input signal INTP0 interrupt request Cleared by software Captured D1 D0 D2 CE1 1 ...

Page 186: ...4 3 2 1 0 0 0 1 0 0 CRC1 Disables clearing TM1 when TM1 coincides with CR10 Specifies the CR11 register as a capture register Clearing TM1 when TM1 is captured to CR11 is disabled 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 1 TMC1 Overflow flag Enables counting TM1 7 6 5 4 3 2 1 0 PRS10 0 PRM1 PRS12 PRS11 Specifies count clock x fCLK where x 16 32 64 128 256 or 512 7 INTM0 0 1 6 5 4 3 2 1 0 Specifies valid edge...

Page 187: ...ister and MK0L register CRC1 04H X0 0 CE1 1 Initialize buffer memory for capture value Start counting Sets bit 3 of TMC1 to 1 Enable interrupt INTP0 interrupt Specifies valid edge of INTP0 input to be both edges and unmasks interrupt Pulse width measurement Set PRM1 register INTP0 interrupt Calculation of pulse width Store captured value in memory RETI Xn 1 CR11 Yn CR11 Xn ...

Page 188: ...nter 1 Interval timer Whenoperatingasanintervaltimer 8 bittimer counter2generatesaninternalinterruptatspecifiedintervals Table 7 11 Intervals of 8 Bit Timer Counter 2 Resolution 16 fCLK 2 6 µs 32 fCLK 5 3 µs 64 fCLK 10 7 µs 128 fCLK 21 3 µs 256 fCLK 42 7 µs 512 fCLK 85 3 µs Maximum interval 28 16 fCLK 683 µs 28 32 fCLK 1 37 ms 28 64 fCLK 2 73 ms 28 128 fCLK 5 46 ms 28 256 fCLK 10 9 ms 28 512 fCLK ...

Page 189: ... 256 fCLK 42 7 µs 512 fCLK 85 3 µs The values in parentheses are based on fCLK 6 MHz Caution The values in Table 7 12 assume the use of an internal clock 3 Pulse width measurement Eight bit timer counter 2 measures the pulse width of a signal applied to the external interrupt input pin INTP1 Table 7 13 Pulse Width Measurement Range of 8 Bit Timer Counter 2 Measurable pulse width 28 16 fCLK 683 µs ...

Page 190: ...t registers for holding a value that determines the period of interval timer operation When the values of the CR20 and CR21 registers coincide with the value of TM2 interrupt requests INTC20 INTC21 and timer output control signals are generated Count value clear operation can also be performed when the value of CR21 coincides with the value of TM2 The CR20 and CR21 registers allow both read and wr...

Page 191: ... CLK 64 f CLK 32 f CLK 16 Prescaler mode register PRM1 8 RESET Internal bus 8 bit timer 2 TM2 Capture trigger Capture register CR22 8 Clear Overflow Coincidence Coincidence 8 Compare register CR21 Compare register CR20 8 MOD1 MOD0 CLR22 CLR21 8 Timer control register TMC1 CE2 OVF2 CMD2 PWM PPG output control Capture compare control register CRC2 ENT03 ALV3 ENT02 ALV2 P36 TO2 P37 TO3 Output control...

Page 192: ...8 Bit Timer Counter 2 Control Registers 1 Timer control register 1 TMC1 The TMC1 register is an 8 bit register for controlling the count operations of 8 bit timer 1 TM1 and 8 bit timer 2 TM2 Thehigher4bitscontrolthecountoperationofTM2of8 bittimer counter2 Thelower4bitscontrolthecount operation of TM1 of 8 bit timer counter 1 The TMC1 register allows both read and write operations using an 8 bit ma...

Page 193: ...n Fig 7 68 shows the format of the PRM1 register When the RESET signal is applied the PRM1 register is cleared to 00H Fig 7 68 Format of Prescaler Mode Register 1 PRM1 PRS23 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 1 1 1 Specification of count clock Hz fCLK 16 fCLK 32 fCLK 64 fCLK 128 fCLK 256 fCLK 512 85 3 s 42 7 s 21 3 s 10 7 s 5 3 s 2 6 s Resolution fCLK 6 MHz These bit...

Page 194: ... 1 0 MOD1 0 1 CLR21 0 0 CRC2 Toggle output Toggle output Toggle output Toggle output Toggle output Timer output mode Clearing TM2 PWM output PPG output Does not clear Clears when the TM2 register coincides with the CR21 register Clears when the TM2 register coincides with the CR21 register or after contents of TM2 is caped to the CR22 register TO2 TO3 MOD1 MOD0 CLR22 CLR21 Clears after contents of...

Page 195: ...hen the RESET signal is applied the TOC register is cleared to 00H Fig 7 70 Format of Timer Output Control Register TOC 7 6 5 4 3 2 1 0 ENTO3 ALV2 ENTO1 ENTO0 ALV0 TOC ALV3 ENTO2 ALV1 These bits control timer output operation output of pins TO0 and TO1 by the 16 bit timer counter see Fig 7 5 Active level for TO2 pin When toggle output is specified When toggle output is specified When PWM PPG outpu...

Page 196: ...ck pulse then capture operation and coincide with signal generation stop If the CE2 bit is set to 1 when the CE2 bit is already set to 1 TM2 count operation is not affected See Fig 7 71 b If the count clock signal is applied when the value of TM2 is FFH TM2 is set to 00H At this time OVF2 is set and the overflow signal is sent to the output control circuit OVF2 can be cleared only by software Coun...

Page 197: ...eans that even if a TM2 clear cause occurs TM2 holds the value existing at that time until the next count clock pulse is applied Fig 7 72 TM2 Cleared by a Coincidence with Compare Register CR21 Count clock fCLK 8 TM2 Cleared by software OVF2 OVF2 0 FEH FFH 0H 1H Count clock Compare register CR21 TM2 n 1 n 0 1 Coincidence between TM2 and CR21 Cleared here n Fig 7 73 TM2 Cleared after Capture Operat...

Page 198: ...e the first count clock pulse is applied after the CE2 bit is reset to 0 two operations are simultaneously performed one operation is an operation to clear TM2 to 0 and the other operation is a count operation starting with the counting of 0 Fig 7 74 Clear Operation When the CE2 Bit Is Reset to 0 a Basic operation TM2 CE2 n 1 n 0 Count clock b Restart after 0 is set in TM2 cleared Count clock TM2 ...

Page 199: ...external clock pulse that can be counted by TM2 functioning as an external event counter is 187 5 kHz when occurrences of both CI input signal edges are counted and is 250 kHz when occurrences of only one edge are counted fCLK 6 MHz When occurrences of both edges are counted the external clock pulse signal must have a pulse width of 16 system clock pulses 2 67 µs fCLK 6 MHz or more for both the hi...

Page 200: ...detector 2 When occurrences of both edges are counted maximum frequency fCLK 32 Count clock of TM2 Dn 2 32 fCLK Min 16 fCLK Min 16 fCLK Min 16 fCLK constant CI ICI Countable timing of TM2 TM2 Dn 1 Dn Dn 3 Dn 4 Dn 5 8 12 fCLK Remark ICI CI input signal after passing through the edge detector CI ICI Count clock of TM2 Countable timing of TM2 TM2 Dn Dn 1 Dn 2 Dn 3 16 fCLK constant 12 fCLK Min 12 fCLK...

Page 201: ...dition the generation of an interrupt request by a coincidence with a compare register CR20 CR21 lags the input of an edge Take this point into consideration when short period timing control is required after input of an edge Fig 7 76 Interrupt Request Generation Using External Event Counter Countable timing of TM2 TM2 n n 1 n 1 ICI CI 8 to 12 clocks 16 clocks Max Count clock of TM2 INTP2 occurs h...

Page 202: ...d Edge with External Event Counter Cannot be distinguished TM2 1 0 2 CI 0 Count starts Fig 7 78 How to Distinguish Input of No Valid Edge from Input of Only One Valid Edge with External Event Counter a Count start processing Count starts Clear INTP2 interrupt request flag Clears PIF2 0 Start counting Sets CE2 1 End TMC1 7 1 IF0L 2 0 ...

Page 203: ...ed edge At this time an interrupt request is also generated on the edge When other in circuit emulators are used Count operation is not performed on an erroneously detected edge However an interrupt request is generated on the edge For detailed information about erroneous edge detection see Section 11 4 Reads count value Read contents of TM2 Check TM2 value If 0 check interrupt request flag Check ...

Page 204: ...M2isclearedto00Hbythefirstcountclockpulse thencount upoperation starts When the value of TM2 reaches FFH full count as the result of count operation bit 6 OVF2 of the TMC1 register is set to 1 and TM2 stops its count operation with the count value of FFH held From the count stop state one shot timer operation can be started again by resetting the OVF2 bit to 0 by software When the OVF2 bit is rese...

Page 205: ...INTC20 INTC21 are generated After the value of the CR21 register coincides with a count value of TM2 the count value of TM2 can be cleared Thus 8 bit timer counter 2 can operate as an interval timer for repeatedly counting up to the value set in the CR21 register Fig 7 80 Compare Operation Remark CLR21 0 CLR22 0 CE2 1 OVF2 TM2 count value Count starts Value of CR21 Value of CR20 Value of CR20 Valu...

Page 206: ... undefined A valid edge used as a capture trigger is set using external interrupt mode register 0 INTM0 When both a rising edge and falling edge are set as capture triggers the pulse width of an applied external signal can be measured When a capture trigger is generated using one edge the period of an input pulse signal can be measured For the detailed format of the INTM0 register see Fig 11 1 in ...

Page 207: ...n TM2 count value n 0 1 2 CLR21 0 CLR22 0 D0 D1 D2 D0 D1 D2 undefined undefined Reads CR22 Reads CR22 FFH TM2 count value Capture register CR22 INTP1 interrupt request INTP1 pin input 0H Count starts CE 1 OVF2 CPU operation Interrupt accepted Interrupt accepted ...

Page 208: ...om the compare registers The operation of the output control circuit is determined by timer output control register TOC and capture compare control register 2 CRC2 See Table 7 15 Before a timer output TO0 or TO1 signal can be output on a pin the pin must be placed in the control mode by the PMC3 register Captured Captured Captured Captured Captured Capture compare register CR22 N4 N5 N3 N2 N1 0H T...

Page 209: ...high active Tied high low PWM output high low active PWM output high low active Tied high low Toggle output low high active Toggle output low high active Tied high low Toggle output low high active Tied high low Toggle output low high active PWM output high low active Tied high low PWM output high low active PWM output high low active Tied high low PWM output high low active PPG output high low ac...

Page 210: ...an operation mode where the level of output is inverted each time the value of a compare register CR20 CR21 coincides with the value of 8 bit timer 2 TM2 The output level of TO2 is inverted when the value of CR20 coincides with the value of TM2 The output level of TO3 is inverted when the value of CR21 coincides with the value of TM2 When8 bittimer counter2isstoppedbyresettingtheCE2bitoftheTMC1reg...

Page 211: ...ontrol register 2 CRC2 must be set to 0 and the CMD2 bit of timer control register 1 TMC1 must be set to 0 The pulse period and pulse width are as follows PWM period 256 x fCLK PWM pulse width value set in compare registerNote x 2 fCLK x 16 32 64 128 256 512 Note Zero cannot be set in the compare registers Duty factor PWM pulse width PWM period value set in compare register x 2 256 x value set in ...

Page 212: ...2 7 5 3 10 7 21 3 42 7 85 3 PWM period ms 0 7 1 4 2 7 5 5 10 9 21 8 PWM frequency Hz 1465 732 366 183 92 46 Fig 7 86 shows an example of 2 channel PWM output Fig 7 87 shows PWM output when FFH is set in the CR20 compare register Fig 7 86 Example of PWM Output Using TM2 FFH CR20 CR20 CR20 CR21 CR21 TM2 count value 0H INTC20 INTC21 TO2 TO3 FFH FFH Remark ALV2 0 ALV3 0 ...

Page 213: ...utput the output levels on the timer outputs TO2 TO3 are not inverted Fig 7 88 Example of Rewriting a Compare Register TO2 T1 T2 T1 T1 T1 T2 T2 FFH TM2 count value 0H CR20 Rewriting CR20 TO2 does not change though CR20 coincides with TM2 FFH FFH Remark ALV2 1 FFH INTO20 TO2 TM2 count value Count clock period T OVF flag Duty factor 100 99 6 0 1 2 0 1 2 0 Pulse width Pulse period 256T 255 256 T FFH ...

Page 214: ...er and has a pulse width determined by the CR20 compare register PPG output is PWM output whose period is made variable This output signal can be output on the TO0 pin only Before this function can be used the CLR21 bit of capture compare control register 2 CRC2 must be set to 1 the CLR22 bit of the same register must be set to 0 and the CMD2 bit of timer control register 1 TMC1 must be set to 0 T...

Page 215: ... 64 fCLK 128 fCLK 256 fCLK 512 Minimum pulse widthNote 2 67 µs 5 33 µs 10 7 µs 21 3 µs 42 7 µs 85 3 µs PPG period 5 33 µs to 683 µs 10 7 µs to 1 37 ms 21 3 µs to 2 73 ms 42 7 µs to 5 46 ms 85 3 µs to 10 9 ms 171 µs to 21 8 ms PPG frequency 187 5 kHz to 1 46 kHz 93 75 kHz to 732 Hz 46 9 kHz to 366 Hz 23 4 kHz to 183 Hz 11 7 kHz to 91 6 Hz 5 86 kHz to 45 8 Hz Note The case where CR20 0 is excluded C...

Page 216: ...0 CR21 Remark ALV2 0 Fig 7 92 PPG Output When CR20 00H Remark ALV2 0 1 2 n n n INTC20 INTC21 TO2 TM2 count value n 1 0 n 1 2 1 0 0 Count period T Pulse period n 1 T Pulse width nT T 1 2 n n n INTC20 INTC21 TO2 TM2 count value 0 Pulse period n 1 T Pulse width 2 fCLK ...

Page 217: ...mark ALV2 1 Cautions 1 If a value less than the value of 8 bit timer 2 TM2 is written into the CR20 compare register before the value of CR20 coincides with the value of TM2 a PPG signal with a 100 duty factor is output in that period Rewrite CR20 if required by using an interrupt generated by a coincidence between TM2 and CR20 Fig 7 94 Example of PPG Output Signal with a 100 Duty Factor TO2 CR20 ...

Page 218: ...ut and normal PPG output is resumed Rewrite CR21 if required by using an interrupt generated by a coincidence between TM2 and CR21 Fig 7 95 Example of PPG Output Period Made Longer n3 n1 n2 n4 n2 0H CR20 CR21 TO2 n1 n3 n1 n4 n2 Full count value n3 n5 TM2 count value The PPG period is extended when a value n2 less than TM2 value n5 is written to CR21 here TO2 becomes inactive when CR20 coincides wi...

Page 219: ...mpare registers so that interval timers with two types of periods can be produced Fig 7 97 shows the setting of control registers Fig 7 98 shows the setting procedure Fig 7 99 shows interrupt handling Fig 7 96 Timing of Interval Timer Operation 1 n n 0H TM2 count value MOD 2n MOD 3n FFH MOD 2n MOD 3n MOD 4n Timer starts Compare register CR20 INTC20 interrupt request Rewriting by inter rupt program...

Page 220: ... Timer control register 1 TMC1 Fig 7 98 Setting Procedure for Interval Timer Operation 1 Interval timer 1 Set count value in CR20 register Set CRC2 register Set TMC1 register Sets bit 7 of TMC1 to 1 Sets normal mode CMD2 0 INTC20 interrupt CE2 1 CMD2 0 CRC2 10H CR20 n Set PRM1 register 7 6 5 4 3 2 1 0 PRS23 0 PRM1 Specifies count clock x fCLK where x 16 32 64 128 256 512 or external clock PRS22 PR...

Page 221: ...Fig 7 101 shows the setting of control registers and Fig 7 102 shows the setting procedure Fig 7 100 Timing of Interval Timer Operation 2 Remark Interval n 1 x fCLK 0 n FFH x 16 32 64 128 256 512 INTC20 interrupt Other interrupt program CR20 CR20 n RETI Calculation of timer value at which next interrupt is to occur 0H TM2 count value n Compare register CR21 INTC21 interrupt request Interrupt accep...

Page 222: ...ontrol register 1 TMC1 7 6 5 4 3 2 1 0 PRS23 0 PRM1 Specifies count clock x fCLK where x 16 32 64 128 256 512 or external clock PRS22 PRS21 PRS20 7 6 5 4 3 2 1 0 1 0 0 0 0 0 TMC1 Normal mode Overflow flag Enables counting 7 6 5 4 3 2 1 0 0 1 CRC2 Enables clearing TM2 when CR21 coincides with TM2 0 0 1 0 0 0 Disables clearing TM2 when TM2 captured Both TO2 and TO3 are used for toggle output ...

Page 223: ...7 103 the value of 8 bit timer 2 TM2 in count operation is loaded and held in the CR22 capture register on a valid edge either a rising edge or falling edge of a signal applied to the INTP1 pin The pulsewidthoftheinputsignalisfoundbymultiplyingthecountclockbythedifferencebetweentheTM2count value Dn loaded and held in the CR22 register on the n th valid edge detected and the TM2 count value Dn 1 lo...

Page 224: ... register 2 CRC2 7 CRC2 0 0 6 5 4 3 2 1 0 0 1 0 0 0 0 Disables clearing TM2 7 6 5 4 3 2 1 0 PRS23 0 PRM1 Specifies count clock x fCLK where x 16 32 64 128 256 512 or external clock PRS22 PRS21 PRS20 OVF2 Capture register CR22 TM2 count value 0H Captured Captured D1 D0 X fCLK Captured Count starts D0 D1 D2 D3 D3 D2 X fCLK 100H D1 D2 X fCLK D3 FFH FFH INTP1 external input signal INTP1 interrupt requ...

Page 225: ... Initialize buffer memory for capture value Enable interrupt INTP1 interrupt Specifies valid edge of INTP1 input to be both edges and unmasks interrupt Pulse width measurement Set TMC1 register Sets bit 7 of TMC1 to 1 Sets normal mode CMD2 0 CE2 1 CMD2 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 TMC1 Normal mode Overflow flag Enables counting 7 INTM0 0 1 6 5 4 3 2 1 0 Specifies valid edge of INTP1 input to be r...

Page 226: ...s of 1 256 from 1 256 to 255 256 In addition 8 bit timer 2 TM2 has two compare registers so that two types of PWM signals can be output Fig 7 108 shows the setting of control registers Fig 7 109 shows the setting procedure Fig 7 110 shows the procedure for changing the duty factor of PWM output Fig 7 107 Example of PWM Signal Output by 8 Bit Timer Counter 2 FFH FFH FFH Timer starts 0H TM2 count va...

Page 227: ... TM2 Both TO2 and TO3 are used for PWM output d Timer output control register TOC e Port 3 mode control register PMC3 7 6 5 4 3 2 1 0 1 0 0 0 0 0 TMC1 Normal mode Overflow flag Enables counting for TM2 7 6 5 4 3 2 1 0 PRS23 PRM1 Specifies count clock x fCLK where x 16 32 64 128 256 or 512 PRS22 PRS21 PRS20 7 6 5 4 3 2 1 0 1 TOC 0 TO3 for high active PWM signal output Enables PWM output for TO3 7 6...

Page 228: ...or of PPG output Fig 7 111 Example of PPG Signal Output by 8 Bit Timer Counter 2 Timer starts 0H TM2 count value active high TO2 CR20 CR20 CR20 CR21 CR21 CR21 PWM output Set CRC2 register Set TOC register Set P34 pin in control mode Set initial value in compare register Set count clock in PRM1 CRC2 90H PMC3 4 1 Start counting Sets bit 7 of TMC1 CE2 1 CIF21 0 Preprocessing for changing duty factor ...

Page 229: ...clearing when TM2 is captured by CR22 register TO2 is used for PPG output d Timer output control register TOC e Port 3 mode control register PMC3 7 6 5 4 3 2 1 0 PRS23 PRM1 Specifies count clock x fCLK where x 16 32 64 128 256 or 512 PRS22 PRS21 PRS20 7 6 5 4 3 2 1 0 1 0 0 0 0 0 TMC1 Normal mode Overflow flag Enables counting for TM2 7 6 5 4 3 2 1 0 1 TOC 0 TO2 for high active PWM signal output En...

Page 230: ...shows the setting of control registers and Fig 7 117 shows the setting procedure when 8 bit timer counter 2 functions as an external event counter Remark The value of TM2 is less then the number of input clock pulses by 1 PPG output Set CRC2 register Set TOC register Set P34 pin in control mode Set period in compare register CR21 Set count clock in PRM1 CRC2 D8H PMC3 6 1 Set duty factor in compare...

Page 231: ...MC1 Fig 7 117 Setting Procedure for External Event Counter Operation 7 6 5 4 3 2 1 0 1 1 1 0 PRM1 1 Specifies external clock input C1 7 6 5 4 3 2 1 0 0 INTM0 1 Specifies valid edge of C1 input as rising edge 7 6 5 4 3 2 1 0 1 0 0 0 0 0 TMC1 Normal mode Overflow flag Enables counting Event counter Specify valid edge of C1 pin input Set PRM1 register Start counting Sets bit 7 of TMC1 to 1 PRM1 0F H ...

Page 232: ... setting procedure Fig 7 121 shows the procedure for starting an additional one shot operation Fig 7 118 One Shot Timer Operation b Prescaler mode register 1 PRM1 c Capture compare control register 2 CRC2 7 6 5 4 3 2 1 0 0 CRC2 1 0 0 0 0 0 0 Disables clearing TM2 Fig 7 119 Setting of Control Registers for One Shot Timer Operation a Timer control register 1 TMC1 0H INTC21 OVF2 OVF2 0 Count starts C...

Page 233: ...on One shot timer Set one shot timer mode Sets bit 5 of TMC1 to 1 Set PRM1 register Set count value in CR21 register Set CRC2 register Start counting Sets bit 7 of TMC1 to 1 INTC21 interrupt CE2 1 CRC2 10H CR21 n CMD2 1 Restarting one shot timer Set count value in CR21 register Restart counting Clears bit 6 of TMC1 to 0 INTC21 interrupt CR21 n OVF2 0 ...

Page 234: ...r 3 Resolution 8 fCLK 1 3 µs 16 fCLK 2 6 µs 32 fCLK 5 3 µs 64 fCLK 10 7 µs 128 fCLK 21 3 µs 256 fCLK 42 7 µs 512 fCLK 85 3 µs Maximum interval 28 8 fCLK 341 µs 28 16 fCLK 683 µs 28 32 fCLK 1 37 ms 28 64 fCLK 2 73 ms 28 128 fCLK 5 46 ms 28 256 fCLK 10 9 ms 28 512 fCLK 21 8 ms Minimum interval 8 fCLK 1 3 µs 16 fCLK 2 6 µs 32 fCLK 5 3 µs 64 fCLK 10 7 µs 128 fCLK 21 3 µs 256 fCLK 42 7 µs 512 fCLK 85 3...

Page 235: ...eration of TM3 can be enabled or disabled by timer control register 0 TMC0 When the RESET signal is applied TM3 is cleared to 00H and count operation stops 2 Compare registers CR30 The CR30 register is an 8 bit registers for holding a value that determines the period of interval timer operation When the value of the CR30 register coincides with the value of TM3 the value of TM3 is automatically cl...

Page 236: ...tops counting Enables counting 0 1 TM3 counting control These bits control counting for 16 bit timer counter TM0 see Fig 7 3 CE3 2 Prescaler mode register 0 PRM0 The PRM0 register is an 8 bit register used to specify a count clock for 8 bit timer 3 TM3 The PRM0 register allows only write operation using an 8 bit manipulation instruction Fig 7 124 shows the format of the PRM0 register When the RESE...

Page 237: ...er 3 When the CE3 bit is set to 1 by software TM3 is cleared to 00H by the first count clock pulse then count up operation starts When the CE3 bit is reset to 0 TM3 is cleared to 00H by the next count clock pulse then coincide with signal generation stops If the CE3 bit is set to 1 when the CE3 bit is already set to 1 TM3 is not cleared but continues count operation Fig 7 125 Basic Operation of 8 ...

Page 238: ...ence between TM3 and CR30 Cleared here n TM3 can also be cleared by software when the CE3 bit of the timer control register TMC0 is reset to 0 Similarly clear operation is performed by the count clock pulse following the resetting of CE3 bit to 0 If the CE3 bit is set to 1 before TM3 is reset to 0 by the resetting of the CE3 bit to 0 that is before the first count clock pulse is applied after the ...

Page 239: ...CE3 1 are performed simultaneously n 0 1 2 7 4 5 Compare Register Operation Eight bit timer counter 3 performs a compare operation to compare the value set in the compare register with a timer count value When the value set in the compare register CR30 coincides with a count value of 8 bit timer 3 TM3 the interrupt request INTC30 is generated After the value of the CR30 register coincides with a c...

Page 240: ...µs and 21 8 ms respectively at internal system clock fCLK 6 MHz Fig 7 129 shows the timing of interval timer operation Fig 7 130 shows the setting of control registers for interval timer operation Fig 7 131 shows the setting procedure Fig 7 129 Timing of Interval Timer Operation Remark Interval n 1 x fCLK 0 n FFH x 8 16 32 64 128 256 512 0H TM3 count value n Compare register CR30 INTC30 interrupt ...

Page 241: ...MCn is set the counter can malfunction The cause of such a malfunction is that when a hardware function change made by the rewriting of a register conflicts with a state change of the function before the rewriting which change is to have priority is undefined Before rewriting these registers be sure to stop counter operation for safety Prescaler mode register PRMn Capture compare control register ...

Page 242: ...TMm Example To prevent the OVF1 flag of timer counter 1 from being cleared MOV A TM1 MOV TMC1 xxx01000B xxx depends on the manipulation of timer counter 2 CMP A TM1 Checks the timer value BL NEXT BE NEXT MOV TMC1 xxx011000B Sets OVF1 NEXT 3 If the value of a compare register coincides with the value of a timer register when an instruction for stopping timer operation is executed the count operatio...

Page 243: ...top the timer Even if a timer is started CEn 1 before the timer is cleared to 0 immediately after the timer is stopped the timer counts up starting with 0 Fig 7 133 Count Operation Stop Fig 7 134 Timing of Count Operation Stop and Restart Count clock Actual counting starts Count start instruction by software CEn 1 TMn n 0 to 3 CEn 0 0 1 2 3 Count clock TMn n 0 to 3 m m 1 0 Count stop CEn 0 Counter...

Page 244: ... to 3 For example if the value of the CRnm register remains unchanged after the CRnm is written to no interrupt request is generated and timer output TOn n 0 to 3 does not change even when the value of TMn coincides with the value of the CRnm register While a timer counter is performing count operation CRnm register write operation must be performed when the value of TMn does not coincide with the...

Page 245: ...peration must be performed using an interrupt generated by a coincidence between TMn and CRnm to be rewritten Fig 7 135 Example of PWM Output Signal with a 100 Duty Factor TOp p 0 2 CRnm 0H n1 n2 n2 n2 n2 n3 n1 TMn count value When a value n2 less than TMn value n3 is written to CRnm here the duty factor is 100 during this period n1 FFFFHorFFH FFFFHorFFH FFFFHorFFH FFFFHorFFH Remark ALVp 0 ...

Page 246: ...n1 CRn1 CRn1 CRn1 CRn1 Remark ALVp 0 b If the current value of the CRn1 compare register is decreased below the value of TMn the PPG period becomes as long as the full count time of TM2 At this time if CRn1 is rewritten after the value of the CRn0 compare register coincides with the value of TMn the inactive level is output until TMn overflows to 0 then normal PPG output is resumed If CRn1 is rewr...

Page 247: ... approximate value by two clock pulses of fCLK for the inactive level Take this point into consideration when high precision output is required or a high speed count clock is used For details see Section 7 1 7 and Section 7 3 9 12 Iftimeroutputisdisabled ENTOn 0 n 0 1 or2 3 theoutputlevelontheTOn n 0 1 or2 3 istheinverted value of the value set in ALVn n 0 1 or 2 3 Accordingly note that if timer o...

Page 248: ...ter does not coincide with the value of the compare register Normal coincidence based interrupt generation is resumed when a normal edge is applied or the timer counter is stopped Timer output is not affected by an erroneously detected edge but is performed with the normal timing For details of erroneous edge detection see Section 11 4 When using an in circuit emulator see also Section 7 5 4 7 5 2...

Page 249: ...one cannot distinguish between the state where no valid edge is applied and the state where only one valid edge has been applied See Fig 7 139 In either case the value of TM2 is 0 When the states need to be distinguished from each other use the INTP2 interrupt request flag The same pin is used as the INTP2 pin as well as the CI pin so that the functions can be used at the same time Fig 7 140 shows...

Page 250: ... Count value read processing Count starts Clear INTP2 interrupt request flag Clears PIF2 0 Start counting Sets CE2 1 End TMC1 7 1 IF0L 2 0 Reads count value Read contents of TM2 Check TM2 value If 0 check interrupt request flag Check contents of PIF2 If 1 valid edge has been input End The number of valid edges input to register A is set IF0L 2 1 Yes Yes No A A 1 A TM2 A 0 No ...

Page 251: ... R is used All timer counter related operations are performed on erroneously detected edges in the same way as on normal edges 2 When other in circuit emulators are used a Capture operation Capture operation is not performed on an erroneously detected edge However an interrupt is generated on an erroneously detected edge The value of a capture register read during interrupt handling performed on a...

Page 252: ...r other than IE 78210 R Interrupt generation timing when CRnm n2 n 1 2 m 0 1 Interrupt generation timing when CRnm n1 n 1 2 m 0 1 n1 n2 n1 Interrupt is generated here by the effect of an erroneously detected edge Interrupt request is not generated by the effect of an erroneously detected here Interrupt request is generated by the effect of an erroneously detected edge Erroneous edge detection µ µ ...

Page 253: ...nd the value of a compare register becomes faster by the number of edges detected erroneously The timer output function is not affected by an erroneously detected edge but operates with the correct timing Such an interrupt generation timing deviation as described above can be corrected by the following operations Clear operation on a normal edge when the clear function following capture operation ...

Page 254: ...e started the A D converter operates in either of the following modes Scan mode Analog inputs are sequentially selected for A D conversion from all the input pins Select mode Only one input pin is used Analog signals are successively input from this pin to the converter These start and operating modes are specified by the ADM register The ADM register is also used to stop conversion When the conve...

Page 255: ...eries resistor string Input selector Tap selector R 2 R 2 A D converter mode register ADM Voltage comparator AV SS R AV REF Selector INTAD INTP5 RESET Interrupt request 8 8 8 Trigger enable Conversion trigger Control circuit Edge detector Internal bus A D conversion result register ADCR INTP5 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ...

Page 256: ...s the input analog signal voltage The series resistor string is connected between the reference voltage pin AVREF and the GND pin AVSS of the A D converter It consists of 255 resistors each having equal resistance and two resistors each having half the resistance of the other 255 resistors This configuration enables the voltage between the AVREF and AVSS pins to be divided into 256 steps A voltage...

Page 257: ... to enable external synchronization for A D conversion When the TRG bit is set to 1 if the CS bit is already 1 the conversion is initialized each time a valid edge arrives at the INTP5 pin as an external trigger When the TRG bits is reset to 0 conversion is carried out regardless of the state of the INTP5 pin Bit 7 CS controls A D conversion When this bit is set to 1 the A D converter starts opera...

Page 258: ...mode Scans AN0 input Scans AN0 and AN1 inputs Scans AN0 to AN2 inputs Scans AN0 to AN3 inputs Scans AN0 to AN4 inputs Scans AN0 to AN5 inputs Scans AN0 to AN6 inputs Scans AN0 to AN7 inputs Selects AN0 input Selects AN1 input Selects AN2 input Selects AN3 input Selects AN4 input Selects AN5 input Selects AN6 input Selects AN7 input Controls conversion speed 180 fCLK Note 120 fCLK Note fCLK 4 MHz f...

Page 259: ...ignal voltage A voltage tap of the serial resistor string is selected as follows according to the state of bit 7 which has already been set according to the result Bit 7 1 383 512 AVREF 3 4 AVREF Bit 7 0 127 512 AVREF 1 4 AVREF The voltage at this tap is compared with the input analog voltage According to the comparison result bit 6 of the SAR register is set or reset as follows Analog input volta...

Page 260: ...h AN7 are related to the A D conversion result value held in the ADCR as follows ADCR INT 256 0 5 or ADCR 0 5 VIN ADCR 0 5 Remark INT Function returning the integer part of a value specified in VIN Analog input voltage AVREF AVREF pin voltage ADCR Value in the ADCR register Fig 8 5 shows the relations between the analog voltages and the A D conversion results Fig 8 5 Relations between Analog Input...

Page 261: ...6 µs to 12 µs System clock fCLK range FR bit Conversion time Sampling time 8 3 2 Select Mode Bits 1 through 3 ANI0 through ANI2 of the ADM register specify one analog input pin A D conversion is repeated for the specified pin The resultant digital data is stored in the A D conversion result register ADCR If bit 6 TRG of the ADM register is set to enable an external trigger an A D conversion end in...

Page 262: ...d INTAD Conversion end AN1 AN2 AN0 AN0 AN1 AN0 AN0 AN1 AN0 INTP5 Initialization CS 1 MS 0 ANI2 0 010 Conversion starts Initialization Initialization Initialization Cautions 1 When the result of A D conversion is read by using a vectored interrupt during the scan mode if the A D conversion end interrupt is kept pending for a prolonged time because of other interrupts being handled at least 180 cloc...

Page 263: ...opped and another A D conversion sequence that matches the newly written value is started immediately Once A D conversion is started the conversion sequence of the new data is started according to the mode of operation specified in the ADM register immediately when the conversion sequence of the previous data is completed A D conversion continues until a write instruction is executed for the ADM r...

Page 264: ...lue When a valid edge arrives conversion starts By using this function A D conversion can be synchronized with an external signal When one A D conversion sequence is completed another conversion sequence is started immediately in an operating mode set in the ADM register the converter does not wait for the input from the INTP5 pin Conversion continues until an instruction that writes to the ADM re...

Page 265: ...as been specified that A D conversion be hardware started A D conversion may be started by an erroneously detected edge See Section 11 4 for detail on erroneous detection of an edge 1 Select mode A D conversion The analog signal at the input pin specified in the ADM register is converted to digital form When one A D conversion sequence is completed the analog signal at the same input pin is conver...

Page 266: ... Remark n 0 1 7 m 0 1 7 2 Scan mode A D conversion When A D conversion is started the analog signal input to the AN0 pin is converted When one conversion sequence is completed the signal from the next analog input pin is converted Each time a conversion sequence is completed an interrupt request INTAD is generated WhenavalidedgearrivesattheINTP5pinduringA Dconversion thecurrentconversionsequenceis...

Page 267: ...by Hardware AN0 AN2 AN1 AN0 AN0 AN1 AN2 AN1 AN0 AN1 AN0 AN0 AN0 AN2 AN1 AN0 ADCR AN0 ADM writing CS 1 TRG 1 A D conversion scans AN0 to AN2 Standby state INTP5 pin input rising edge valid INTAD INTAD accepted AN1 AN2 AN0 Standby state ADM rewriting CS 1 TRG 1 AN2 AN1 ...

Page 268: ...rnal weight according to the MM and PW registers Specify P66 as an input port PM66 1 Do not use an internal pull up resistor PUO6 0 2 When using AN7 Inhibit refresh RFEN 0 Specify P67 as an input port PM67 1 Do not use an internal pull up resistor PUO6 0 8 6 NOTES 1 Range of voltages applied to analog input pints When using the A D converter input pins AN0 through AN7 P66 P67 P70 through P75 obser...

Page 269: ...e input pin AVREF and the AVSS pin Fig 8 13 Example of Capacitors Connected to the A D Converter Pins 4 When using the STOP mode reset the CS bit to 0 beforehand to reduce supply current If the CS bit remains set to 1 conversion do stops when the STOP mode is selected but power supply to the voltage comparator is not stopped Consequently the supply current to the A D converter does not decrease 5 ...

Page 270: ...the following measures Keep the time required to handle other interrupts adequately shorter than the required A D conversion time Use the multiplexed interrupt mode so that the A D conversion end interrupt can be accepted even when other interrupts are being handled Use a macro service to handle the A D conversion end interrupt NotethattheA Dconversionendinterruptmayalsobekeptpendingbythecausesdes...

Page 271: ...242 ...

Page 272: ... wide baud rate range In addition a baud rate can also be specified by dividing the frequency of the clock input to the ASCK pin Moreover 8 bit timer counter 3 can be used to generate a baud rate When the baud rate generator for UART is used the MIDI standard baud rate 31 25 kbps can also be obtained The asynchronous serial interface operates independently of the clock synchronized serial interfac...

Page 273: ...INTSER ASIS Transmission control parity generation P31 TxD P30 RxD 1 16 1 16 Selector Transmission shift register Asynchronous serial interface status register RXE PSI PS0 CL SL SCK RESET ASIM Asynchronous serial interface mode register 1 8 Shift register Reception control parity check 1 2 8 bit timer counter 3 output UART baud rate generator output ...

Page 274: ...S become undefined 3 Shift register The shift register converts the serial data input to the RxD pin into parallel data When it receives 1 byte of data it sends it to the reception buffer The shift register cannot be manipulated directly from the CPU 4 Reception control parity check Reception is controlled according to the contents of the asynchronous serial interface mode register ASIM In additio...

Page 275: ...et to 1 when a reception error occurs It is reset to 0 by reading data from the reception buffer When the next data is received the overrun error flag OVE is set to 1 and the other error flags are reset to 0 if this new data also contains an error the error flag corresponding to that error is set to 1 Both 8 bit manipulation instruction and bit manipulation instruction can be used for the ASIS reg...

Page 276: ...gister and baud rate generator or timer counter 3 If an error occurs during reception of serial data the error can be identified by reading the contents of the asynchronous serial interface status register ASIS 9 3 2 Parity Types and Operations The parity bit is used to detect a bit error in transmit receive data Usually the same parity bit is used at both the transmission and reception ends When ...

Page 277: ...cally When transmission is triggered the transmission shift register TXS shifts out its contents When the register becomes empty a transmission completion interrupt INTST occurs If no further transmission data is written to the transmission shift register TXS transmission breaks Fig 9 5 Asynchronous Serial Interface Transmission Completion Interrupt Timing START D0 D1 D2 D6 D7 Parity STOP STOP D6 ...

Page 278: ... not affected and neither INTSR nor INTSER is generated Setting the RXE bit to 1 triggers sampling for a start bit Note Reception assumes there is only one stop bit regardless of whether the SL bit of the ASIM register is 1 Fig 9 6 Asynchronous Serial Interface Reception Completion Interrupt Timing STOP D6 Parity D7 D2 D1 D0 START RxD Input INTSR Cautions 1 If the ASIM register is modified during ...

Page 279: ...dentifies it by detecting that a framing error has occurred twice consecutively where the receive data is 00H Software can differentiate the break signal from a sequence of two accidental framing errors This is done by reading the level of the RxD pin by reading port 3 P3 by setting bit 0 of the port 3 mode register to 1 and checking if it is 0 Cautions 1 The ASIS register is reset to 0 when the r...

Page 280: ...for details of edge detection 9 4 2 Baud Rate Generator Control Register BRGC The BRGC register is an 8 bit register that holds the clock for baud rate generation controlled according to the internal system clock fCLK Only an 8 bit manipulation instruction can be used for this register and its use is limited to write operations Fig 9 9 shows the format of the register When the RESET signal is inpu...

Page 281: ... 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 External clock input ASCK fCLK 4 fCLK 2 fCLK 3 fCLK 4 fCLK 5 fCLK 6 fCLK 7 fCLK 8 fCLK 9 fCLK 10 fCLK 11 fCLK 12 fCLK 13 fCLK 14 fCLK 15 TPS2 TPS1 TPS0 Frequency divider tap 1 n 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 Operations of 4 bit counter...

Page 282: ...ing transmission 1 Generating the baud rate clock from the internal system clock fCLK The internal system clock fCLK is divided by the 4 bit counter The resultant signal is further divided by the frequency divider to generate the baud rate clock The baud rate generated from the internal system clock fCLK is determined by the following formula Baud rate fCLK k 1 1 n 1 16 where fCLK Internal system ...

Page 283: ...er 1 MDL0 through MDL3 of the BRGC register 0H to EH fCLK 61440 fCLK 64 1 n 1 16 fCLK K 1 fCLK 256 fCLK 4194304 fCLK Internal system clock frequency k Value set in the MDL3 through MDL0 bits of the BRGC register k 1 through 14 see Fig 9 9 1 n Frequency divider tap n 2 4 8 16 32 64 128 256 fASCK Frequency of the ASCK input clock 0 fCLK 24 1 16 Serial data sampling rate j Value set in the PRS3 throu...

Page 284: ...H 98H 88H 2 27 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 11 0592 MHz Baud rate error BRGC value 5 5296 MHz FAH F7H E7H D7H C7H B7H A7H 97H 87H 84H 83H 0 89 1 73 1 73 1 73 1 73 1 73 1 73 1 73 1 73 0 00 1 73 10 0 MHz Baud rate error BRGC value 5 0 MHz FAH F7H E7H D7H C7H B7H A7H 97H 87H 84H 83H 0 83 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 1 70 0 00 9 8304 MHz Baud rate error BRGC value 4 9152 MHz FBH ...

Page 285: ... Timer Counter 3 Is Used Table 9 4 lists examples of setting the baud rate when 8 bit timer counter 3 is used When using 8 bit timer counter 3 reset the SCK bit of the asynchronous serial interface mode register ASIM to 0 See Section 7 4 for how to use 8 bit timer counter 3 ...

Page 286: ... 0 00 0 00 0 00 0 00 0 00 11 0592 MHz Baud rate error Count clock 5 5296 MHz m 143 195 143 71 35 17 8 f CLK 16 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 0 16 0 25 0 16 0 16 1 36 1 73 1 73 1 73 1 73 1 73 10 0 MHz Baud rate error Count clock 5 0 MHz m 129 177 129 64 32 15 7 3 1 0 f CLK 16 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 f CLK 8 0 00 0 26 ...

Page 287: ...gister becomes empty but no transmission completion interrupt occurs Transmission is triggered by writing the transmit data to the transmission shift register 3 The ASIS register is reset to 0 when the reception buffer RXB is read accessed or receives the next data To identifytheerror besuretochecktheASISbeforereadingdatafromtheRXB Ifamacroserviceisusedduring reception it is impossible to identify...

Page 288: ... interface SBI mode MSB first In this mode the device can communicate with two or more devices via two lines the serial clock SCK and serial data bus line SB0 This mode conforms to the NEC serial bus format In SBI mode an address for selecting a target device for serial communication a command specifying the operation of the target device and actual data can be output on the serial data bus This m...

Page 289: ...tor INTCSI Interrupt signal generator circuit Bus release command acknowledge detector circuit Serial clock counter Serial clock control circuit N ch open drain output enabled Selector P32 SCK P33 SO SB0 P27 SI RESET CTXE CRXE WUP MOD1 CLS1 CLS0 1 8 CSIM ACKT CMDD RELD CMDT RELT ACKE ACKD BSYE 1 8 SBIC 8 Shift register SIO RESET Busy acknowledge output circuit Q SO latch SET CLEAR ...

Page 290: ...k to be used 4 Serial clock counter Counts the number of serial clock pulses output or input during transmission or reception and checks whether 8 bit data is transmitted or received 5 Interrupt signal generator Controls whether an interrupt request is generated when the serial clock counter counts eight serial clock pulses In three wire serial I O mode an interrupt request is generated each time ...

Page 291: ...SBI mode 8 bit timer counter 3 output 2 Input 1 0 1 1 fCLK 32Note 2 fCLK 8Note 2 Output Slave Master WUP 3 wire serial I O mode Operation mode 0 0 MOD1 0 1 Controls wakeup function SBI mode 1 1 Generates interrupt request at each serial transfer Generates interrupt request only when address is received CRXE Disabled Reception 0 1 Enabled CTXE Disabled Transmission 0 1 Enabled Notes 1 Always write ...

Page 292: ...anipulationinstructionmanipulatethecontentsoftheregister These bits have different read write attributes listed in Table 10 1 When the contents are read 0 is read from the write only bits The format is shown in Fig 10 3 The register is set to 00H when RESET is input Detection flags ACKD CMDD and RELD are cleared when transmission and reception are inhibited both CTXE and CRXE are set to 0 Table 10...

Page 293: ...CMD 0 Not output 1 Output RELD Detection of bus release signal REL 0 Not detected 1 Detected CMDD Detection of command signal CMD 0 Not detected 1 Detected ACKT Trigger output control for acknowledge signal ACK 0 Not output 1 Output ACKE Permission of acknowledge signal ACK automatic output 0 Prohibited 1 Permitted ACKD Detection of acknowledge signal ACK 0 Not detected 1 Detected BSYE Permission ...

Page 294: ...K SI SO Port Interrupt port Note Master CPU Slave CPU Note Handshaking line 10 4 1 Basic Operation Timing In three wire serial I O mode data is transmitted and received in units of eight bits The data is transmitted and received one bit at a time by means of the MSB first method in synchronization with the serial clock The transmission data is output in synchronization with the falling edge of SCK...

Page 295: ...up resistor to pin P33 SO Fig 10 6 Sample Connection with a Device Having Two Wire Serial I O SCK 2 wire serial I O device SI SO SCK SIO PD78214 µ If transmission and reception are time shared and if the µPD78214 can control the output level of the SIO pin of a device containing two wire serial I O the SI pin and SO pin can be connected directly To do this disable transmission by other devices whi...

Page 296: ...itted Reception is performed when the CRXE bit of the CSIM register is set 1 When the CRXE bit is changed from 0 to 1 or when the contents of the SIO are read reception is started 1 Selecting the internal clock as the serial clock When reception is started the serial clock is output from the SCK pin In synchronization with the rising edge of the serial clock data is sequentially sent from the SI p...

Page 297: ...ception is inhibited the contents of the SIO become undefined If transmission and reception are simultaneously inhibited transmission and reception are halted and the subsequent SCK input is ignored If this occurs the contents of the SIO become undefined No interrupt request INTCSI is issued The output from the SO pin goes to the high impedance state 10 4 5 Action to Be Taken When the Serial Clock...

Page 298: ...ignal to check whether the serial data has been received 5 Busy signal BUSY control function This function controls the busy signal that indicates that a slave device is busy Fig 10 7 shows a sample serial bus configured with CPUs having a serial interface conforming to SBI and peripheral ICs In SBI mode serial data bus pin SB0 functions as an open drain output pin The serial data bus lines are wi...

Page 299: ...er CMOS push pull output Slave Schmitt input 2 SB0 Input output pin for serial data For both master and slave N ch open drain output or Schmitt input The serial data bus line requires an external pull up resistor because of the N ch open drain output pin Fig 10 8 Pin Configuration SO RL SI SO SI SB0 SB0 Serial data bus N ch open drain N ch open drain Clock input Clock output Clock input Clock outp...

Page 300: ...circuit Bus release command acknowledge detector circuit Serial clock counter Serial clock control circuit N ch open drain output enabled Selector P32 SCK P33 SO SB0 P27 SI RESET CTXE CRXE WUP MOD1 CLS1 CLS0 1 8 CSIM ACKT CMDD RELD CMDT RELT ACKE ACKD BSYE 1 8 SBIC 8 Shift register SIO RESET Busy acknowledge output circuit Q SO latch SET CLEAR CLS1 CLS0 MPX 8 bit timer counter 3 output 1 2 ...

Page 301: ...match the software releases the wake up state sets WUP to 0 and prepares for the reception of the subsequent command and data 10 5 4 Control Registers in SBI Mode 1 Clock synchronous serial interface mode register CSIM This 8 bit register specifies a serial interface operation mode serial clock and wake up function Fig 10 10 shows the format of the CSIM register The 8 bit manipulation instruction ...

Page 302: ... as shown below Example Changing CTXE from 1 to 0 and CRXE from 0 to 1 CLR1 CTXE SET1 CRXE CTXE 7 CRXE 6 WUP 5 0 4 MOD1 3 0 2 CLS1 1 CLS0 0 CSIM CLS1 Internal clock External clock Selects serial clock 0 0 CLS0 0 1 SCK pin Master slave selection in SBI mode 8 bit timer counter 3 output 2 Input 1 0 1 1 fCLK 32 fCLK 8 Input Slave Master WUP 3 wire serial I O mode Operation mode 0 0 MOD1 0 1 Controls ...

Page 303: ...BSYE 7 ACKD 6 ACKE 5 ACKT 4 CMDD 3 RELD 2 CMDT 1 RELT 0 SBIC 00H when RESET is input Trigger output control bit for the bus release signal REL When this bit is set the SO latch is set to 1 then the RELT bit is automatically cleared to 0 RELT Trigger output control bit for the command signal CMD When this bit is set the SO latch is cleared to 0 then the CMDT bit is automatically cleared to 0 CMDT 1...

Page 304: ...lls first time after releasing busy after the transfer start instruction has been executed 2 When RESET signal is input 3 CTXE CRXE 0 Clearing condition ACKD 0 Setting condition ACKD 1 When acknowledge signal ACK is detected 4 When bus release is detected in slave mode only Cautions ACKE Disables automatic output of acknowledge signal Before transfer After transfer 0 Outputs ACK in synchronization...

Page 305: ...ation of Shift Register and Related Components In the SBI data bus configuration the same pins are used for both input and output The output pin functions as an N ch open drain output pin With an external pull up resistor the output pin has a wired OR configuration For a device that is going to receive data set the shift register SIO to FFH Alternatively disable transmission by the device Internal...

Page 306: ...ase signal Command transfer Command signal Data transfer The master device outputs the bus release signal and command signal The slave device outputs BUSY Either the master or slave device can output ACK Usually the device receiving 8 bit data outputs ACK The master device continues serial clock output during the period from the start of 8 bit data transfer to the release of BUSY 10 6 1 Bus Releas...

Page 307: ... 1 2 3 4 5 6 7 8 Address A7 A6 A5 A4 A3 A2 A1 A0 Command signal Bus release signal The 8 bit data output following the bus release signal and command signal is defined as an address In a slave device the hardware detects the condition and the hardware or software checks whether the 8 bit data matches its own number slave address If the 8 bit data matches a slave address the slave device is selecte...

Page 308: ...ynchronized with the SCK clock pulse at a desired position After sending the 8 bit data the transmitting device checks whether the receiving device returns the acknowledge signal If the receiving device does not return the acknowledge signal within a certain period after the data is sent the device has not successfully received the data The 8 bit data following the command signal is defined as a c...

Page 309: ...he slave is busy The busy signal is output after the acknowledge signal is output by the master or slave device The busy signal is set or released in synchronization with the falling edge of SCK When the busy signal is released the master device automatically terminates the output of the SCK serial clock The master device can start the next transfer when the busy signal is released and the ready s...

Page 310: ...SB0 ACK ACKT ACK signal is output during first clock cycle immediately after ACKT is set When set during this period SCK 1 2 7 8 D7 D6 D2 D1 SB0 D0 9 ACK ACKE When ACKE 1 at this point The ACK signal is output during the ninth clock cycle SCK 6 7 8 9 D2 D1 D0 SB0 ACK ACKE The ACK signal is output during the first clock cycle immediately after ACKT is set When ACKE is set during this period and ACK...

Page 311: ...his period and ACKE 0 at the falling edge of SCK D2 D1 D0 SIO SCK 9 8 D2 D1 D0 SB0 ACKD 7 6 ACK Transfer start request Transfer operation start D7 D6 b When the ACK signal is output after the ninth pulse of the SCK clock SIO SCK D2 D1 D0 SB0 ACKD 9 ACK 8 7 6 Transfer start request Transfer operation start D7 D6 c Clear timing when a transfer start is specified in the busy state SIO SCK D2 D1 D0 SB...

Page 312: ...Clock Synchronous Serial Interface 10 Fig 10 26 BSYE Operation SCK SB0 BSYE 9 BUSY 8 7 6 ACK When BSYE 1 at this point When reset operation is executed during this period and BSYE 0 at the falling edge of SCK D2 D1 D0 ...

Page 313: ...ition RELT is set CMDT is set Output condition RELD is set CMDD is clear ed CMDD is set Influence on flag Description Following this signal the CMD signal is output to indicate that the transmission data is an address 1 If this signal is output after the REL signal the transmission data is an address 2 If this signal is output without the REL signal the transmission data is a command Signal name T...

Page 314: ...nition 1 ACKE is set to 1 2 ACKT is set BSYE is set to 1 1 BSYE is set to 0 2 When CTXE is set to 1 data is written into the SIO a serial transfer start is specified Note 2 3 When CTXE is set to 0 and CRXE is set to 1 the instruction to read data from the SIO is executed 4 The CRXE bit is changed from 0 to 1 Output condition ACKD is set Influence on flag Description Reception is completed Because ...

Page 315: ... signal is output without the REL signal 8 bit data transferred in synchronization with SCK when neither the REL signal nor CMD signal is output Serial clock SCK Address A7 to A0 Command C7 to C0 Data D7 to D0 Output device Definition Output condition CSIIF is set at the rising edge of the eighth clock pulse Note 1 Influence on flag Description Timing of signal output to the serial data bus Addres...

Page 316: ...e methods of releasing the BUSY state Table 10 3 Conditions Governing Release of BUSY Divice and condition CTxE 0 0 1 1 CRxE 0 1 0 1 BSYE 0 SIO read access BSYE 0 SIO write accessNote Conditions governing the release of BUSY Note Write FFH into the SIO if the next operation is reception 10 6 10 Setting Wake Up If WUP is set to 1 in the busy state the wake up state is set as soon as the device ente...

Page 317: ...receiver Interrupt handling preparation for next serial transfer Set ACKD Serial transmission Generate INTCSI Clear BUSY Serial reception Output BUSY Clear BUSY BUSY Set CMDT Set RELT Set CMDT Write to SIO Stop SCK Read SIO Set ACKT Set CMDD Clear CMDD Set RELD Set CMDD Generate INTCSI Output ACK Compare addresses Remark This timing is valid only under the following conditions The master is only a...

Page 318: ... Transfer line Slave device processing receiver Interrupt handling preparation for next serial transfer Serial transmission Generate INTCSI Serial reception Generate INTCSI Output BUSY Clear BUSY BUSY Set CMDT Write to SIO Set ACKD Stop SCK Read SIO Analyze command Set ACKT Clear BUSY Set CMDD Output ACK Remark This timing is valid only under the following conditions The master is only allowed to ...

Page 319: ...tter Transfer line Slave device processing receiver Interrupt handling preparation for next serial transfer Serial transmission Generate INTCSI Serial reception Generate INTCSI BUSY Write to SIO Set ACKD Stop SCK Read SIO Set ACKT Clear BUSY Output BUSY Output ACK Clear BUSY Remark This timing is valid only under the following conditions The master is only allowed to transmit data The slave is onl...

Page 320: ...ster device processing receiver Transfer line Slave device processing transmitter Read SIO Read SIO Set ACKT Receive data processing Stop SCK Serial reception Generate INTCSI Output ACK Serial reception Write to SIO Write to SIO Clear BUSY Serial transmission Generate INTCSI Set ACKD Output BUSY Clear BUSY 3 D5 Remark This timing is valid only under the following conditions The master is only allo...

Page 321: ...ge will be terminated before the eighth bit is sent To change these statuses use two instructions as shown below Example Changing CTXE from 1 to 0 and CRXE from 0 to 1 CLR1 CTXE SET1 CRXE 2 When switching the master and slave the input and output of the serial clock line SCK are asynchronously switched between the master and slave The serial clock line SCK requires a pull up resistor 3 Do not set ...

Page 322: ... D converter INTM0 INTM1 Register specifying the edge to be detected The edge detection function is always enabled except in STOP mode The edge detection function of pin P20 is enabled even in STOP mode 11 1 EXTERNAL INTERRUPT MODE REGISTERS INTM0 INTM1 The external interrupt mode registers INTM0 INTM1 specify the valid edge to be detected on pins P20 to P26 The INTM0 register specifies the valid ...

Page 323: ... trigger 0 ES00 0 ESNMI Falling edge Specifies edge to be detected on P20 NMI 0 1 Rising edge Rising edge 0 1 Inhibited 1 0 Both falling and rising edges 1 1 ES11 Falling edge Specifies edge to be detected on P22 INTP1 CR22 capture trigger 0 ES10 0 Rising edge 0 1 Inhibited 1 0 Both falling and rising edges 1 1 ES21 Falling edge Specifies edge to be detected on P23 INTP2 CI input 0 ES20 0 Rising e...

Page 324: ...ited 1 0 Both falling and rising edges 1 1 ES41 Falling edge Specifies edge to be detected on P25 INTP4 0 ES40 0 Rising edge 0 1 Selects INTC30 1 0 Both falling and rising edges 1 1 ES51 Falling edge Specifies edge to be detected on P26 INTP5 A D conversion start signal 0 ES50 0 Rising edge 0 1 Inhibited 1 0 Both falling and rising edges 1 1 Caution If an edge is input while a valid edge is changi...

Page 325: ... P20 an edge is detected up to 10 µs after it is actually input This pin differs from pins P21 to P26 in that the delay depends on the characteristics of the device 10 s Max µ 10 s Max µ 10 s Min µ Rejected as noise because pulse is too narrow Falling edge is detected because pulse is sufficiently wide Rising edge is detected because pulse is sufficiently wide Rejected as noise because pulse is to...

Page 326: ... clock to detect an edge after the edge is actually input 2 If the width of an input pulse corresponds to 8 to 12 cycles of the fCLK clock it cannot be determined whether the pulse is detected as a valid edge To ensure the accurate detection of a pulse hold the pulse at an identical level for 12 clock cycles or longer 3 If noise input to a pin is synchronized with the fCLK 4 clock of the µPD78214 ...

Page 327: ...h that when the values of the timer counter and compare register match If the mode for performing a clear operation after a capture operation is selected the timing of match interrupt generation can be cor rected by inputting a correct edge or by stopping the timer counter If timer counter 2 is used as an external event counter the timing of the match interrupt generation can be corrected by stopp...

Page 328: ...usly detected edge fCLK 4 After noise rejection Falling edge detection Rising edge detection Noise L b Erroneously detected edge during input of high signal INTPn input n 0 to 6 Erroneously detected edge fCLK 4 After noise rejection Falling edge detection Rising edge detection Noise L If the IE 78210 R is used the real time output port timer counter and A D converter operate according to the erron...

Page 329: ...ation will disagree with that when the values of the timer counter and compare register match If the mode for performing a clear operation after a capture operation is selected the timing of match interrupt generation can be corrected by inputting a correct edge or by stopping the timer counter If timer counter 2 is used as an external event counter the timing of match interrupt generation can be ...

Page 330: ...ed in Table 12 1 Table 12 1 Interrupt Request Handling Modes Interrupt request handling mode Processed by Vectored interrupt Macro service Processing PC and PSW contents Saved and restored Retained Program control branches to a specified service program Predetermined processing such as data transfer between memory and I O is performed Software Hardware firmware Maskable vectored interrupts can eas...

Page 331: ...mis sion end INTCSI clock synchronized serial interface transmission end Macro service type None None A B A B A B B B B A B C A B C A B B A B B A B A B None A B A B A B Vector table address 003EH 0002H 0006H 0008H 000AH 000CH 0014H 0016H 0018H 001AH 001CH 0012H 0020H 0022H 0024H 0026H 000EH 0010H Interrupt request source Generating unit Default priority Edge detection 16 bit timer counter 8 bit ti...

Page 332: ...ctor table interrupt request flags and other control flags Therefore either INTP4 or INTC30 must be selected by software The same holds true of a pair of INTP5 and INTAD A selected interrupt request source is given the right to use the vector table interrupt request flags PIFn n 4 or 5 interrupt mask flags PMKn n 4 or 5 interrupt service mode flags PISMn n 4 or 5 and priority specification flags P...

Page 333: ...d PSW The IF0 MK0 ISM0 and PR0 are 16 bit read write registers The contents of these registers can be manipulated in either 16 or 8 bit units In addition each bit of these registers can be set and reset by a bit manipulation instruction independently of the other bits The IST and PSW are 8 bit read write registers whose contents can be manipulated in either 8 or 1 bit units The IE flag in the PSW ...

Page 334: ... PPR1 PPR2 PPR3 CPR00 CPR01 CPR10 CPR11 CPR21 CPR20 SERPR SRPR STPR CSIPR PIF4 PIF5 PMK4 PISM4 PISM5 PPR4 PPR5 PMK5 12 2 1 Interrupt Request Flag Register IF0 The IF0 register is a 16 bit register consisting of interrupt request flags Each interrupt request flag is set to 1 when the corresponding interrupt request occurs It is reset to 0 when a vectored interrupt is accepted or macro service proce...

Page 335: ...t to 0000H thereby specifying vectored interrupt handling Fig 12 5 Interrupt Service Mode Register ISM0 Format 12 2 4 Priority Specification Flag Register PR0 The PR0 register is a 16 bit register consisting of interrupt priority specification flags that determine priority with which each interrupt is accepted They are used to control multiple interrupt handling There are two interrupt groups with...

Page 336: ...able interrupt request is accepted if the NMIS bit is 0 it is not accepted if the NMIS bit is 1 The NMIS bit is set to 1 when a nonmaskable interrupt request is accepted It is reset to 0 when a return execution of the RETI instruction from the interrupt handling for the nonmaskable interrupt request occurs Both an 8 bit manipulation instruction and bit manipulation instruction can be used to read ...

Page 337: ...HANDLING 12 3 1 Accepting Software Interrupts A software interrupt request is accepted by executing the BRK instruction Software interrupts cannot be disabled When a software interrupt request is accepted the PSW and PC are saved in the stack in the stated order the IE flag is reset to 0 and the PC is loaded with the contents of the vector table at 003EH and 003FH to cause a branch The RETB instru...

Page 338: ...terrupt service program is running Fig 12 9 Accepting an NMI Interrupt Request a If a new NMI request occurs during execution of an NMI service program when the IST register is not manipulated Main routine NMIS 1 NMI request pending because NMIS 1 Processing pending NMI request NMI request NMI request b If a new NMI request occurs during execution of an NMI service program when the NMIS bit is res...

Page 339: ...or example by executing the EI instruction in the nonmaskable interrupt service program maskableinterruptrequestsassignedhighpriorityaremadeacceptable Ifamaskableinterruptwithhighpriorityoccursduring execution of the nonmaskable interrupt service program a service program for the maskable interrupt runs If the IE and ISP bits of the PSW are set to 1 interrupt requests with low priority will also o...

Page 340: ... single instruction after a reset resulting in a program crash almost with no exception To avoid these problems initialize the stack pointer after a reset and design the hardware so that the NMI signal does not drop within 10 µs 20 fCLK after the RESET signal rises 12 3 3 Accepting Maskable Interrupts A maskable interrupt is accepted when the corresponding interrupt request flag is set to 1 if the...

Page 341: ...rrupts occur simultaneously No ISM 0 Yes IE 1 Yes Vectored interrupt processing Is there a high priority interrupt among interrupts for PR 0 that have occurred simultaneously Interrupt request pending Macro service processing Interrupt request pending Interrupt request pending Interrupt request pending Interrupt request pending Macro service processing Interrupt request pending Interrupt request p...

Page 342: ...upt Nonmaskable interrupt Maskable interrupt by macro service processing Nonmaskable interrupt All maskable interrupts Nonmaskable interrupt Maskable interrupt by macro service processing Nonmaskable interrupt Maskable interrupt by macro service processing Maskable interrupt assigned high programmable priority Nonmaskable interruptNote 2 Maskable interrupt by macro service processing Nonmaskable i...

Page 343: ...t e high priority Vectored interrupt request a low priority Processing b Processing c Processing d Macro service request b Macro service request d Vectored interrupt request c high priority Processing e Processing f Processing h Processing g Macro service request h Macro service request f EI Nesting 1 Nesting 2 Nesting 3 Vectored interrupt request g low priority Pending EI ...

Page 344: ...st l low priority Pending Processing l Processing m Vectored interrupt request n low priority Pending Processing o Vectored interrupt request p low priority Pending Processing n Processing p Processing s Processing q Vectored interrupt request r low priority Pending Processing r EI Setting EI ISP to 1 EI Vectored interrupt request j low priority Vectored interrupt request j high priority Vectored ...

Page 345: ...egisters related to interrupts do not specify this BF instruction as the branch destination Otherwise all interrupts and macro services are kept pending until a condition that inhibits a branch is met during execution of the instruction Example of incorrect coding LOOP BF IF0H 3 LOOP Example of correct coding 1 LOOP NOP BF IF0H 3 LOOP Main routine Processing b Nesting 1 Nesting 2 Processing d Proc...

Page 346: ... services pending Fig 12 13 Interrupt Request Generation and Acceptance Unit Clock Interrupts or macro services will not be kept pending long because they are processed after the BR is executed Remark The BTCLR would be more convenient than the BT because it clears the flags automatically 2 Interrupt request acceptance time The time listed in Table 12 5 is required to accept each interrupt request...

Page 347: ...rocessing type With ring control A B w number of wait cycles Note The time listed here does not include the time that elapses before the current instruction is completed or the time required to identify the priority of the interrupt request Remarks 1 The values in the Internal ROM fetch column apply when the IFCH bit of the memory expansion mode register MM is 1 If the IFCH bit is 0 see the Extern...

Page 348: ...vice function a vectored interrupt can be generated after processing has been performed a specified number of times so that the vectored interrupt program can be simplified Fig 12 14 Differences between a Vectored Interrupt and Macro Service Notes 1 This timing chart applies when the register bank switching function is used and the registers are loaded with the initial values in advance 2 The PC a...

Page 349: ... register used for type A CR11 CR22 TM2 CR10 CR11 CR21 CR30 ACDR CR20 RxB TxB SIO Interrupt request source Generating unit 8 bit timer counter 2 Edge detection 8 bit timer counter 3 Edge detection A D converter 8 bit timer counter 2 Edge detection 16 bit timer counter 8 bit timer counter 1 Asynchronous serial interface Clock synchronized serial interface The following three types of macro services...

Page 350: ...12 15 An interrupt request that can specify a macro service is not affected by the state of the IE flag It is disabled by settingtheinterruptmaskflagintheinterruptmaskregister MK0 to1 Themacroserviceprocessingisperformed regardless of whether interrupts are disabled and whether a macro service processing is already being performed Fig 12 15 Macro Service Processing Sequence The type of a macro ser...

Page 351: ...responding to an interrupt request that can be processed by macro service Fig 12 16 Macro Service Control Word Configuration Channel pointer Mode register 0FEDFH 0FEDEH INTSR Channel pointer Mode register 0FEDDH 0FEDCH INTST Channel pointer Mode register 0FEDBH 0FEDAH INTCSI Channel pointer Mode register 0FED9H 0FED8H INTC10 Channel pointer Mode register 0FED7H 0FED6H INTC11 Channel pointer Mode r...

Page 352: ...l pointer specifies the address of a macro service channel The macro service channel can be located in a 256 byte area in the internal RAM at addresses FE00H through FEFFH The higher 8 bits of the address are fixed Therefore the macro service channel pointer specifies the lower 8 bits of the highest address of the macro service channel 12 4 5 Macro Service Type A 1 Operation The type A macro servi...

Page 353: ...ion wait states may be inserted according to the setting of the PW20 and PW21 bits of the memory expansion mode register MM Table 12 9 lists the conditions under which an illegal write access occurs and the corresponding operations Table 12 9 Illegal Write Access Conditions and Corresponding Operations Condition 1 2 Address Address of a destination SFR Address of a source SFR Illegal write access ...

Page 354: ...hannel pointer contents m Read MSC contents n Buffer address calculation m n Identify transfer direction Read contents of buffer and transfer read data to specified SFR MSC n 1 MSC 0 Vectored interrupt request occurs End Read specified SFR contents and transfer read data to buffer Reset interrupt request flag End No Yes Memory SFR SFR memory TYPE A Other factors To other macro service processing ...

Page 355: ...See Fig 12 19 The SFR to be accessed is predetermined for each interrupt request See Table 12 8 Fig 12 19 Type A Macro Service Channel Macro service buffer n MSC n Macro service buffer 2 MSC 2 Macro service buffer 1 MSC 1 Macro service counter MSC Mode register Channel pointer Higher address Lower address Macro service channel Macro service control word Macro service buffer address Channel pointer...

Page 356: ...to memory Data transfer is repeated as many times as previously specified in the macro service counter The macro service transfers 8 bit data The type B macro service can be specified for all interrupt requests of the µPD78214 that can activate a macro service For the type B macro service the SFR pointers can specify any SFRs for data transfer sources and destinations This macro service is a gener...

Page 357: ...sfer direction Read data from SFR and write it to the memory addressed by MP MSC MSC 1 MSC 0 Vectored interrupt request End Read data from memory and write it to the SFR specified by SFR pointer Reset interrupt request flag End No Yes Memory SFR SFR memory TYPE B Other factors To other macro service processing Select transfer source SFR by SFR pointer Select transfer source memory by macro service...

Page 358: ...ice pointer SFR pointer and macro service counter is located at addresses 0FE00H through 0FEFFH in the internal RAM space The channel pointer indicates the macro service channel as shown in Fig 12 22 The channel pointer holds the lower 8 bits of the address Caution The following registers cannot be used as SFRs IF0L IF0H MK0L MK0H PR0L PR0H ISM0L ISM0H and IST Fig 12 22 Type B Macro Service Channe...

Page 359: ...el Data Input in Synchronization with an External Interrupt Fig 12 24 Parallel Data Input Timing Data input macro service Port 3 INTP4 0A000H 0A01FH Internal RAM 1 Type B Memory SFR Internal bus 0FECFH Mode register Channel pointer A1 CF MSC SFRP MPL low MPH high 00 A0 20 03Note 1 64K memory space Buffer area P37 TO3 P36 TO2 P35 TO1 P34 TO0 P33 SO SB0 P32 SCK P31 TxD P30 RxD Port 3 Edge detector I...

Page 360: ...unction is not used data addressed by the MPT is transferred to the compare register c Ring control This function repeats to output a pattern of data with a predetermined length automatically These ancillary functions are specified in the mode register in the macro service control word Cautions 1 With the type C macro service the MPT and MPD are incremented only at the lower 8 bits If a carry occu...

Page 361: ...register Identify channel type Read channel pointer contents m Read memory addressed by MPT Automatic addition Increment MPTL Yes No Yes TYPE C Other factors To other macro service processing Transfer data to compare register Add data to compare register Retains MPT Read memory addressed by MPD Transfer data to buffer register Increment MPDL 1 No ...

Page 362: ...ectored interrupt request occurs No No Yes No Subtract modulo register contents from low order 8 bits of macro service pointer for data MPDL and return pointer to the first address MSC 0 1 Yes Reload modulo register contents to ring counter End Reset interrupt request flag End Yes MSC MSC 1 ...

Page 363: ...or ring control if used Usually it is initialized with the same value as for the modulo register The macro service counter MSC specifies the number of data transfers to occur The macro service channel holding these pointers and counter is located at addresses 0FE00H through 0FEFFH in the internal RAM space The macro service channel is indicated by the channel pointer as shown in Fig 12 26 The chan...

Page 364: ...ter RC Macro service counter MSC Data macro service pointer low MPDL Data macro service pointer high MPDH Timer macro service pointer low MPTL Timer macro service pointer high MPTH Mode register Channel pointer Macro service channel Macro service control word Higher address Lower address ...

Page 365: ...put port Fig 12 27 Open Loop Control for a Stepper Motor by the Real Time Output Port 0FECFH MPTH high B0 MPTL low 04 MPDH high B0 MPDL low 00 MSC 04 Mode register Channel pointer E8 CF internal RAM 1 Type C Increment Internal bus 1 1 Output data area 0B007H T3 T2 T1 D4 D3 D2 D1 T4 64K memory space 0B004H 0B003H 0B000H Output timing data area Macro service control word Compare register CR10 8 bit ...

Page 366: ...a pattern must be prepared even if more data patterns are required Therefore the required data ROM area can be kept small The macro service counter MSC is decremented each time one data transfer is performed The ring control function also generates an interrupt request when MSC 0 Let s take an example of controlling a stepping motor The data pattern output to the steeping motor varies with the str...

Page 367: ...tepping Motor with Phase 1 Excitation Fig 12 30 Four Phase Stepping Motor with Phases 1 and 2 Excitation 1 2 3 4 1 2 3 1 cycle 4 patterns Phase A Phase B Phase C Phase D 1 8 2 3 4 5 6 7 8 1 2 3 4 5 1 cycle 8 patterns Phase A Phase B Phase C Phase D ...

Page 368: ...r RC 08 1 Modulo register MR 08 MPDL 00 1 MPDH B0 MPTL 00 MPTH B1 Mode register CE Channel pointer CF 0FECFH Macro service control word Macro service channel D0 D1 D7 t Compare register CR10 P00 Output latch Coincidence INTC10 P0 8 bit timer counter 1 TM1 Addition Buffer register P0L 0B000 0B001 0B007 Output data 8 pieces Output timing 0B100 64K memory space P01 P02 P03 To stepper motor ...

Page 369: ...tation with Phases 1 and 2 Excitation T0 T2 T1 t T3 T2 t T4 T3 t T5 T4 t T6 T5 t T7 T6 t T8 T7 t T9 T8 t T10 T9 t D0 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 t FFH Count starts 0H TM1 count value INTC10 Compare register CR10 Buffer register P0L P00 P01 P02 P03 T1 T0 t Remark Select a mode in which the MPT contents are retained ...

Page 370: ...ister MR 04 MPDL 00 1 MPDH B0 MPTL 00 MPTH B1 Mode register EE Channel pointer CF Macro service control word Macro service channel D0 D1 D7 t0 Compare register CR10 P00 Output latch Coincidence INTC10 P0 8 bit timer counter 1 TM1 Addition Buffer register P0L 0B000 0B001 0B007 Output data 4 pieces Output timing 0B100 64K memory space P01 P02 P03 To stepper motor 0FECFH t1 tFF Macro service control ...

Page 371: ...g Varied by Phase 2 Excitation t9 T1 T0 t1 T2 T1 t2 T3 T2 t3 T4 T3 t4 T5 T4 t5 T6 T5 t6 T7 T6 t7 T8 T7 t8 T9 T8 t9 T0 D2 D3 D0 D1 D2 D3 D0 D1 D2 D1 t8 t6 t5 t4 t3 t1 t2 T0 0H TM1 count value INTC10 Compare register CR10 Buffer register P0L P00 P01 P02 P03 t7 Count starts FFH Remark Select a mode which increments the MPT ...

Page 372: ...dling program and except a period between a special instruction described inSection 12 3 5 and an instruction that follows that special instruction Therefore nonmaskable interrupts are accepted even if the contents of the stack pointer are undefined for example right after a reset occurs At this point the contents of the PC and PSW may be transferred to addresses see Table 3 4 in Section 3 2 5 whe...

Page 373: ...expansion mode register MM Table 12 9 lists the conditions under which an illegal write access occurs and the corresponding operations Table 12 12 Illegal Write Access Conditions and Corresponding Operations Condition Macro service type 1 2 3 A A C Address Address of a destination SFR Address of a source SFR Address of a destination SFR CR10 or CR11 Illegal write access Data Data transferred by ma...

Page 374: ...I Os are accessed by using the RD WR and ASTB signals a multiplexed address data bus consisting of lines AD0 to AD7 and an address bus consisting of lines A8 to A19 Figs 13 3 and 13 4 show the basic bus interface timing diagrams In addition a wait function for interfacing with low speed memory and a refresh signal output function for refreshing pseudo static RAM are provided ...

Page 375: ...0 3 MM2 2 MM1 1 MM0 0 MM MM2 0 0 MM1 0 0 MM0 0 1 PW21 1 0 Number of wait states range 00000H to 0FFFFH 0 0 PW20 0 1 2 1 0 Number of wait states equivalent to low level period of WAIT pin input 1 1 Mode Single chip mode P50 P57 Port mode P40 P47 Input mode P65 Port mode Output mode P65 External memory expansion mode 1 1 1 WR RD A8 A15 AD0 AD7 MM6 Output latch for P60 to P63 P60 to P63 stores higher...

Page 376: ... memory for the µPD78212 56704 byte memory and I Os to be connected according to the setting of the memory expansion mode register MM When the memory space is expanded externally P50 to P57 function as an address bus and P40 to P47 function as a multiplexed address data bus When the EA signal is tied low the µPD78214 operates in ROM less mode In ROM less mode 64768 bytes 65536 bytes for the µPD782...

Page 377: ...D0H to 0FFDFH When manipulating a space in which external device addresses overlap internal RAM or SFR addresses the internal RAM or SFR area is accessed automatically In this case the address signal is output but the ASTB RD and WR signals are not output these signals remain inactive 13 2 2 1M Byte Expansion Function When bit MM6 of the MM register is set to 1 an additional 960K bytes of data mem...

Page 378: ...Program input Lower address output Data input Hi Z Hi Z Hi Z A8 A15 output AD0 AD7 ASTB output Fetch cycle Expansion data memory access cycle b Write cycle RD output A16 A19 output Contents of P6 PM6 register Higher address Higher address Lower address output Hi Z Hi Z Program input Lower address output Data input Hi Z Hi Z A8 A15 output AD0 AD7 ASTB output Fetch cycle Expansion data memory access...

Page 379: ...e A and the transfer data is D0H to DFH 2 Data is transferred from an SFR to memory using macro service Type A and the transfer destination buffer memory address is 0FED0H to 0FEDFH when the macro service is executed 3 The MPTL address is 0FED0H to 0FEDFH when macro service Type C is used An illegal write access is performed in the same way as normal memory access In addition wait states are inser...

Page 380: ...3 6 Data Memory Expansion for µPD78212 When EA L Internal RAM External SFR area SFR 0FD7FH 0FD80H 0FEFFH 0FF00H 0FFD0H 0FFFFH 0FFDFH 00000H MM6 0 External memory Internal RAM External SFR area SFR 10000H MM6 1 External memory Expansion data memory FFFFFH ...

Page 381: ...al memory Internal RAM External SFR area SFR 10000H MM2 MM1 MM0 1 1 1 MM6 1 External memory Expansion data memory FFFFFH Internal ROM Internal ROM MM2 MM1 MM0 1 1 1 MM6 0 Internal RAM External SFR area SFR 00000H Internal ROM MM2 MM1 MM0 0 0 0 or 0 0 1 MM6 0 01FFFH 02000H 0FD7FH 0FD80H 0FEFFH 0FF00H 0FFD0H 0FFDFH 0FFFFH ...

Page 382: ...a Memory Expansion for µPD78213 and µPD78214 When EA L Internal RAM External SFR area SFR 0FCFFH 0FD00H 0FEFFH 0FF00H 0FFD0H 0FFFFH 0FFDFH 00000H MM6 0 External memory Internal RAM External SFR area SFR 10000H MM6 1 External memory Expansion data memory FFFFFH ...

Page 383: ... External memory Internal RAM External SFR area SFR 10000H MM2 MM1 MM0 1 1 1 MM6 1 External memory Expansion data memory FFFFFH Internal ROM Internal ROM MM2 MM1 MM0 1 1 1 MM6 0 Internal RAM SFR 00000H Internal ROM MM2 MM1 MM0 0 0 0 or 0 0 1 MM6 0 03FFFH 04000H 0FCFFH 0FD00H 0FEFFH 0FF00H 0FFD0H 0FFDFH 0FFFFH External SFR area ...

Page 384: ...000A 80000H FFFFFH Since the µPD23C4000A mask programmable ROM requires a long access time insert one wait state by means of the programmable wait function See Section 13 4 The circuit enclosed in dotted lines 74HC375 is required only when an in circuit emulator is used When the emulator is not used remove the 74HC375 and connect Dn and Qn n 1 to 4 respectively If the emulator is used without this...

Page 385: ... Q0 Q7 AD0 AD7 ASTB A8 A14 OE CE A17 A16 A15 A14 A 1 A13 CS WE OE A19 A18 A17 A16 Q4 Q3 Q2 Q1 D4 D3 D2 D1 ST ST G2A C B A G2B WORD BYTE 74HC04 74HC32 O0 O7 I O1 I O8 A0 A14 A0 A14 O0 O7 Y1 Y0 G1 VDD 74HC138 WR RD PD78214 µ 74HC573 74HC375 CE A15 OE Remark Pull up resistors must be connected to the address and address data bus lines ...

Page 386: ...by 1 fCLK 167 ns with fCLK 6 MHz for each wait state There are two methods of inserting wait states Using the programmable wait function to automatically insert a predefined number of wait states and using an external wait signal to control wait insertion Wait state insertion is controlled with the memory expansion mode register MM for space 00000H to 0FFFFH and the programmable wait control regis...

Page 387: ...of µPD78212 When EA L Internal RAM External SFR area SFR 0FD7FH Expansion data memory 00000H External memory 0FD80H 0FEFFH 0FF00H 0FFFFH 10000H 0FFDFH 0FFD0H FFFFFH Space subject to wait control by PW register Space subject to wait control by MM register ...

Page 388: ...nal SFR area SFR 0FD7FH Expansion data memory 00000H External memory 0FD80H 0FEFFH 0FF00H 0FFFFH 10000H 0FFDFH 0FFD0H Space subject to wait control by PW register Space subject to wait control by MM register 01FFFH 02000H Internal ROM Space subject to wait control by MM register only when IFCH bit of MM register is 0 ...

Page 389: ...78213 and µPD78214 When EA L Internal RAM External SFR area SFR 0FCFFH Expansion data memory 00000H External memory 0FD00H 0FEFFH 0FF00H 0FFFFH 10000H 0FFDFH 0FFD0H FFFFFH Space subject to wait control by PW register Space subject to wait control by MM register ...

Page 390: ...l SFR area SFR 0FCFFH Expansion data memory 00000H External memory 0FD00H 0FEFFH 0FF00H 0FFFFH 10000H 0FFDFH 0FFD0H Space subject to wait control by PW register Space subject to wait control by MM register 03FFFH 04000H Internal ROM Space subject to wait control by MM register only when IFCH bit of MM register is 0 FFFFFH ...

Page 391: ...n zero wait states are set Higher address Lower address output Data input Hi Z Hi Z A8 A15 output AD0 AD7 ASTB output RD output Hi Z fCLK Note b When one wait state is set Higher address Lower address output Data input Hi Z Hi Z A8 A15 output AD0 AD7 ASTB output RD output Hi Z fCLK Note ...

Page 392: ...on 13 Fig 13 15 Read Timing of Programmable Wait Function 2 2 c When two wait states are set Higher address Lower address output Data input Hi Z Hi Z A8 A15 output AD0 AD7 ASTB output RD output fCLK Note Note fCLK System clock frequency fXX 2 ...

Page 393: ... a When zero wait states are set Higher address Lower address Data Hi Z Hi Z A8 A15 output AD0 AD7 output ASTB output WR output Hi Z fCLK Note b When one wait state is set Higher address Lower address Data Hi Z Hi Z A8 A15 output AD0 AD7 output ASTB output WR output Hi Z fCLK Note ...

Page 394: ...on 13 Fig 13 16 Write Timing of Programmable Wait Function 2 2 c When two wait states are set Higher address Lower address Data Hi Z Hi Z A8 A15 output AD0 AD7 output ASTB output WR output Hi Z fCLK Note Note fCLK System clock frequency fXX 2 ...

Page 395: ...Higher address Lower address output Data input Hi Z Hi Z A8 A15 output AD0 AD7 ASTB output RD output fCLK Note WAIT input b Write timing Higher address Lower address Data Hi Z Hi Z A8 A15 output AD0 AD7 output ASTB output WR output fCLK Note WAIT input Note fCLK System clock frequency fXX 2 ...

Page 396: ...tion of pseudo static RAM application systems 13 5 2 Refresh Mode Register RFM The RFM register is an 8 bit register that controls the refresh cycle of pseudo static RAM and switching to self refresh The register can be read and written with 8 bit manipulation instructions and bit manipulation instructions Fig 13 18 shows the format of the register When the RESET signal is applied the register is ...

Page 397: ...lse refresh is controlled so that it does not overlap external memory access During the refresh cycle the external memory access cycle is held pending ASTB RD and WR are inactive During the external memory access cycle the refresh cycle is held pending When pulse refresh does not cause a contention with external memory access the refresh cycle can be executed without affecting instruction executio...

Page 398: ...access timing overlaps the refresh pulse output timing therefore the µPD78214 generates a refresh bus cycle of three clock pulses synchronized with the bus cycle Fig 13 20 Pulse Refresh When External Memory Is Accessed a When memory is read b When memory is written Refresh bus cycle Write cycle fCLK fCLK ASTB output WR output REFRQ output Refresh bus cycle Read cycle tCYC tCYC ASTB output RD outpu...

Page 399: ... disabled for approximately 200 nsNote after the output level of pin REFRQ goes high The µPD78214 drives pin REFRQ high synchronized with the refresh timing counter so that refresh pulses are not output during a refresh disabled period To detect pin REFRQ going high the read out level of bit RFLV is set to 1 when pin REFRQ goes high Note This time varies with the speed of the pseudo static RAM Fig...

Page 400: ... peak level of approximately 2 6 V for approximately 10 ns When setting the RFLV bit to 1 follow the steps shown in Fig 13 22 The 200 ns delay after setting RFEN assures the access disabled time when pseudo static RAM returns from self refresh mode Fig 13 22 Return from Self Refresh Clear RFEN bit to 0 Set RFLV bit to 1 Set RFEN bit to 1 Approximately 200 ns delay RFLV 1 Yes No Self refresh mode P...

Page 401: ...A8 to P57 A15 and of P60 A16 to P63 A19 are undefined When designing circuits take this into consideration and make sure that the output of an undefined value will not cause any problems The data sheet of the relevant product gives the specification of the valid period for address output 2 External devices cannot be mapped onto the same addresses as those of the internal RAM area µPD78213 µPD78214...

Page 402: ...ess Transfer destination SFR CR10 or CR11 address Transfer target SFR address This problem can be avoided by applying the following methods 1 The problem caused by condition 1 is difficult to avoid by means of software whether an illegal access occurs depends on the transfer data The problem must be avoided by using the external address decoder so that the area at addresses 0FF00H to 0FFFFH does n...

Page 403: ...glitch may occur on pins A16 to A19 Fig 13 25 Glitch Observed on Pins A16 to A19 during Emulation Approx 2 V Approx 10 ns An n 16 19 RD or WR signal For the RD and WR signals the hold time of the address signals on pins A16 to A19 is almost 0 ns Fig 13 26 Insufficient Address Hold Time during Emulation To prevent these problems it is recommended that a latch be provided for pins A16 to A19 when em...

Page 404: ...375 Chapter 13 Local Bus Interface Function 13 Fig 13 27 Preventing Problems That May Occur during Emulation A19 To target circuit A18 A17 A16 ASTB Q4 Q3 Q2 Q1 D4 D3 D2 D1 Target probe 74HC375 ...

Page 405: ...376 ...

Page 406: ... Program operation Macro service HALT standby STOP standby Interrupt request when interrupts are disabled Vectored interrupt requestNote 1 Set HALT Input RESET Input NMI Vectored interrupt request Note 2 Set STOP Input RESET Input NMI Macro service request 1 byte transfer End of data transfer Note 3 Macro service request 1 byte transfer End of data transfer Note 4 Notes 1 When a vectored interrupt...

Page 407: ...nter 16 bits fxx or fx f CLK STP flip flop 1 Q Q S R STP flip flop 2 Q Q S R HLT flip flop Q Q S R D CK Q PR ISM Macro service request Resets flip flop Sets STOP bit Sets HLT bit CPU CLK Peripheral CLK RAM protect Interrupt control Interrupt request Macro service request ISM EI Overflow Reset NMI RESET 1 2 Oscillation stops CLK ...

Page 408: ...ecute the MOV STBC 01H instruction Caution If HALT mode is specified under the conditions for releasing HALT mode the system does not enter HALT mode instead executing the next instruction or branching to the vectored interrupt service program Clear any interrupt requests before specifying HALT mode to ensure that the system enters HALT mode correctly Table 14 1 Operation States in HALT Mode Clock...

Page 409: ...itions are not satisfied HALT mode is resumed Executing the macro service then resuming HALT mode holding the interrupt request Continuing HALT mode 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 Continuing HALT mode holding the interrupt request Handling a vectored interrupt Note When the NMIS bit of the interrupt status register LST is set to 1 the instruction at the next address is executed Processing then br...

Page 410: ...ent operations depend on the IE flag ISP flag and priority designation flag Table 14 3 Release of HALT Mode by a Maskable Interrupt Request Executing the macro service When the end conditions are satisfied a vectored interrupt is handled When the end conditions are not satisfied HALT mode is resumed Macro service request Executing the instruction at the next address holding the interrupt request E...

Page 411: ...de STOP mode can be released by inputting an NMI or RESET signal 1 Releasing STOP mode by NMI input a Operation The oscillator restarts when an effective edge specified with the external interrupt mode register INTM0 is detected at the NMI pin Then STOP mode is released after the specified time required to allow the oscillation to settle has elapsed Once STOP mode has been released processing bran...

Page 412: ...er Oscillation Settling Time 2 Releasing STOP mode by RESET input The oscillator restarts when the RESET signal is changed from high to low to set the system to the reset state Keep the RESET signal active until the oscillation settling time has elapsed When the RESET signal goes high normal operation starts Unlike ordinary reset the contents of data memory will be the same as those existing immed...

Page 413: ... port is set to control mode setting of the output level is facilitated by changing the setting of the port to port mode 2 Is the input level of each input pin appropriate The voltage input to each pin must be maintained at a level between VSS and VDD A voltage that falls outside this range will result in increased current consumption as well as adversely affecting the reliability of the microcomp...

Page 414: ...TB pin which outputs a low voltage usually does not require any external parts The level of the voltage input to the WAIT pin must be maintained between VSS and VDD Any voltage falling outside this range increases the current consumption as well as adversely affecting the reliability of the microcomputer For the µPD78214 you can prevent problems related to address data bus pins simply by specifyin...

Page 415: ...e the X1 pin is internally short circuited to VSS ground potential to prevent current leakage from the clock oscillator circuit STOP mode must not therefore be specified for a system using an external clock 3 Reset the CS bit for the A D converter before specifying STOP mode 4 The system enters STOP mode even if an NMI request is held when STOP mode is specified When using an NMI request to releas...

Page 416: ...Oscillation Settling Time NMI effective at falling edge 216 fCLK STOP mode Wait for oscillation to settle Normal operation Oscillation settling time is extended by this period CPU operation Count value of oscillation settling time counter Cleared by effctive edge ...

Page 417: ...388 ...

Page 418: ...ss set in the PC You can thus resume the program from an arbitrary address Initialize registers in the program as required The RESET pin contains a noise eliminator based on analog delays to prevent abnormal operation due to noise see Fig 15 1 Fig 15 1 Acceptance of the RESET Signal Remark fCLK System clock frequency fXX 2 When resetting the system at power on keep the RESET signal active until th...

Page 419: ... O I O Output I O I O Input Output During reset Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z After reset state is released Hi Z Hi Z input port Hi Z input port mode Hi Z input port mode Note Hi Z input port mode Note 0 Hi Z input port mode Note Hi Z input port mode Hi Z input port mode 0 Note When ROM less mode is specified EA pin 0 these pins function as an address data bus and output signal...

Page 420: ...10 CR20 CR21 CR30 Capture register CR22 Capture compare register CR11 Timer control registers TMC0 TMC1 Timer output control register TOC CRC0 CRC1 CRC2 Prescaler mode registers PRM0 PRM1 A D converter Mode register ADM A D conversion result register ADCR Undefined Undefined Built in RAM Timer counter unit 16 bit timer counters 8 bit timer counters Capture compare control registers The contents of...

Page 421: ...control register BRGC Real time output port control register RTPC Programmable wait control register PW Refresh mode register RFM Interrupt request flag register IF0 Interrupt mask register MK0 Priority designation flag register PR0 Interrupt service mode register ISM0 Interrupt status register IST External interrupt mode registers INTM0 and INTM1 Standby control register STBC 00H Undefined 80H 00...

Page 422: ...supply voltage reaches the specified level Keep the signal low until oscillation has settled Reset period Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Address output Program input RESET input ASTB output A8 A19 output AD0 AD7 RD output WR output Other I O ports Instruction execution period after reset Reset period Hi Z Hi Z Hi Z RESET input ASTB output P60 P63 output Other I O ports Instruction execution period ...

Page 423: ...394 ...

Page 424: ...ata prepared in memory to the compare register and the buffer register for the real time output port Data transferred to the compare register is used for the interval before the generation of the next interrupt Data transferred to the buffer register is output from port 0 Open loop control of stepper motors with the µPD78214 has the following advantages 1 The real time output function provides acc...

Page 425: ...0H Output latch Output latch Buffer register P0L Real time output port lower Real time output port higher Prescaler mode register Multiplexer Compare register CR10 Match detection interrupt INTC10 Match detection interrupt INTC11 Stepper motor Stepper motor Buffer Buffer P00 P01 P02 P03 P04 P05 P06 P07 f CLK 16 f CLK 32 f CLK 64 f CLK 128 f CLK 256 f CLK 512 ...

Page 426: ... an address for selecting a slave device on the serial bus line Each slave device checks whether the received address is the same as the address assigned to the device using software Only a slave device whose address is the same as the received address returns an acknowledge signal to the master device after which it receives commands from the master device or transfers data to and from the master...

Page 427: ...ta SB0 Address Data Data Data SB0 Address Data Data Command Data SB0 Bus release Command trigger Fig 16 4 Serial Bus Communication Timing A7 A0 8 9 ACK BUSY SCK SB0 C7 C0 8 9 ACK BUSY SCK SB0 READY Address transfer Command transfer D7 D0 8 9 ACK BUSY SCK SB0 READY Data transfer Bus release signal Command signal Selection of slave CPU a feature of SBI ...

Page 428: ... 5 V 6 V NMI RESET VPP VDD CE OE D0 D7 Caution When VPP is 12 5 V and VDD is 6 V CE and OE must not be set to low at the same time 17 2 PROCEDURE FOR WRITING INTO PROM Data can be written into PROM at high speed by following the procedure below 1 Fix the RESET pin to the low level Apply 12 5 V to pin NMI Handle unused pins as described in Section 1 3 2 2 Apply 6 V to the VDD pin and 12 5 V to the ...

Page 429: ... 17 1 Timing Chart for PROM Write and Verify Hi Z Data input A0 A14 Data output Data input Hi Z Hi Z Hi Z 12 5 V D0 D7 VDD Vpp 6 V VDD VDD CE input 3X ms Write Verify Additional write Address input Repetition of X times OE input ...

Page 430: ...to the VDD and VPP pins 3 Input the address of the data to be read into the A0 to A14 pins 4 Set read mode 5 Output the data on the D0 to D7 pins Fig 17 3 is the timing chart for steps 2 to 5 Write failure 25th Write success Last address Last address Write failure up to 24th 1 6 10 7 2 3 4 5 9 Defective device Start writing Apply power supply voltage Set an initial address Verify mode Last address...

Page 431: ...78214 Sub Series Fig 17 3 PROM Read Timing Chart Address input A0 A14 Hi Z Data output CE input OE input D0 D7 Hi Z 17 4 NOTE When VPP is 12 5 V and VDD is 6 V CE and OE must not be set to low at the same time ...

Page 432: ...onal and absolute names Auto increment Auto decrement Immediate data Absolute addressing Relative addressing Bit inversion Indirect addressing Sub bank specification r r Registers Functional name X A C B E D L H Absolute name R0 R7 r1 Register group 1 B C rp rp Register pairs Functional name AX BC DE HL Absolute name RP0 RP3 sfr Special function registers P0 P2 P3 P4 P5 P6 P7 P0H P0L RTPC CR10 CR1...

Page 433: ...ediate data or label byte 8 bit data 8 bit immediate data or label bit 3 bit data 3 bit immediate data or label n Number of shift bits 3 bit immediate data 0 7 RBn Register bank RB0 RB3 18 1 2 Operation Field A Register A 8 bit accumulator X Register X B Register B C Register C D Register D E Register E H Register H L Register L R0 R7 Register 0 to register 7 absolute name AX Register pair AX 16 b...

Page 434: ...ed 8 bit data displacement 128 to 127 Contents at address enclosed in parentheses or at address indicated in register enclosed in parentheses H Hexadecimal number H L Eight high order bits and eight low order bits of 16 bit register pair 18 1 3 Flag Field Blank No change 0 Cleared to zero 1 Set to 1 Set or cleared according to the result R Saved values are restored ...

Page 435: ... r r 2 r r A r 1 A r A saddr 2 A saddr saddr A 2 saddr A saddr saddr 3 saddr saddr A sfr 2 A sfr sfr A 2 sfr A A mem 1 4 A mem A mem 2 5 A mem mem A 1 4 mem A mem A 2 5 mem A A addr16 4 A addr16 A addr16 5 A addr16 addr16 A 4 addr16 A addr16 A 5 addr16 A PSW byte 3 PSW byte PSW A 2 PSW A A PSW 2 A PSW A r 1 A r r r 2 r r A mem 2 4 A mem A mem 3 5 A mem A saddr 2 A saddr A sfr 3 A sfr saddr saddr 3...

Page 436: ... byte 2 A CY A byte saddr byte 3 saddr CY saddr byte sfr byte 4 sfr CY sfr byte r r 2 r CY r r A saddr 2 A CY A saddr A sfr 3 A CY A sfr saddr saddr 3 saddr CY saddr saddr A mem 2 4 A CY A mem A mem 3 5 A CY A mem A byte 2 A CY A byte CY saddr byte 3 saddr CY saddr byte CY sfr byte 4 sfr CY sfr byte CY r r 2 r CY r r CY A saddr 2 A CY A saddr CY A sfr 3 A CY A sfr CY saddr saddr 3 saddr CY saddr s...

Page 437: ...e 4 sfr CY sfr byte CY r r 2 r CY r r CY A saddr 2 A CY A saddr CY A sfr 3 A CY A sfr CY saddr saddr 3 saddr CY saddr saddr CY A mem 2 4 A CY A mem CY A mem 3 5 A CY A mem CY A byte 2 A A byte saddr byte 3 saddr saddr byte sfr byte 4 sfr sfr byte r r 2 r r r A saddr 2 A A saddr A sfr 3 A A sfr saddr saddr 3 saddr saddr saddr A mem 2 4 A A mem A mem 3 5 A A mem A byte 2 A A byte saddr byte 3 saddr ...

Page 438: ...yte sfr byte 4 sfr byte r r 2 r r A saddr 2 A saddr A sfr 3 A sfr saddr saddr 3 saddr saddr A mem 2 4 A mem A mem 3 5 A mem Z AC CY ADDW SUBW CMPW Operation Mnemonic Operand No of bytes Flags AX word 3 AX CY AX word AX rp 2 AX CY AX rp AX saddrp 2 AX CY AX saddrp AX sfrp 3 AX CY AX sfrp AX word 3 AX CY AX word AX rp 2 AX CY AX rp AX saddrp 2 AX CY AX saddrp AX sfrp 3 AX CY AX sfrp AX word 3 AX wor...

Page 439: ...2 A3 0 mem1 3 0 mem1 7 4 A3 0 mem1 3 0 mem1 7 4 mem1 3 A3 0 mem1 3 0 mem1 7 4 A3 0 mem1 3 0 mem1 7 4 mem1 2 A3 0 mem1 7 4 mem1 3 0 A3 0 mem1 7 4 mem1 3 0 mem1 3 A3 0 mem1 7 4 mem1 3 0 A3 0 mem1 7 4 mem1 3 0 Z AC CY INC DEC INCW DECW Operation Mnemonic Operand No of bytes Flags r 1 r r 1 saddr 2 saddr saddr 1 r 1 r r 1 saddr 2 saddr saddr 1 rp 1 rp rp 1 rp 1 rp rp 1 Z AC CY 5 Multiply divide instru...

Page 440: ... 2 X bit CY PSW bit CY 2 PSW bit CY CY saddr bit 3 CY CY saddr bit CY saddr bit 3 CY CY saddr bit CY sfr bit 3 CY CY sfr bit CY sfr bit 3 CY CY sfr bit CY A bit 2 CY CY A bit CY A bit 2 CY CY A bit CY X bit 2 CY CY X bit CY X bit 2 CY CY X bit CY PSW bit 2 CY CY PSW bit CY PSW bit 2 CY CY PSW bit CY saddr bit 3 CY CY saddr bit CY saddr bit 3 CY CY saddr bit CY sfr bit 3 CY CY sfr bit CY sfr bit 3 ...

Page 441: ... CY CY X bit CY PSW bit 2 CY CY PSW bit saddr bit 2 saddr bit 1 sfr bit 3 sfr bit 1 A bit 2 A bit 1 X bit 2 X bit 1 PSW bit 2 PSW bit 1 CY 1 CY 1 1 saddr bit 2 saddr bit 0 sfr bit 3 sfr bit 0 A bit 2 A bit 0 X bit 2 X bit 0 PSW bit 2 PSW bit 0 CY 1 CY 0 0 saddr bit 3 saddr bit saddr bit sfr bit 3 sfr bit sfr bit A bit 2 A bit A bit X bit 2 X bit X bit PSW bit 2 PSW bit PSW bit CY 1 CY CY ...

Page 442: ...P SP 2 1 PCL SP PCH PSW SP 2 R R R SP SP 3 NMIS 0 1 PCL SP PCH PSW SP 2 R R R SP SP 3 PUSH POP MOVW INCW DECW Operation Mnemonic Operand No of bytes Flags PSW 1 SP 1 PSW SP SP 1 sfr 2 SP 1 sfr SP SP 1 rp 1 SP 1 rpH SP 2 rpL SP SP 2 PSW 1 PSW SP SP SP 1 R R R sfr 2 sfr SP SP SP 1 rp 1 rpL SP rpH SP 1 SP SP 2 SP word 4 SP word SP AX 2 SP AX AX SP 2 AX SP SP 2 SP SP 1 SP 2 SP SP 1 Z AC CY BR Operatio...

Page 443: ...if saddr bit 0 sfr bit addr16 4 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 3 PC PC 3 jdisp8 if A bit 0 X bit addr16 3 PC PC 3 jdisp8 if X bit 0 PSW bit addr16 3 PC PC 3 jdisp8 if PSW bit 0 saddr bit addr16 4 PC PC 4 jdisp8 if saddr bit 1 then reset saddr bit sfr bit addr16 4 PC PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 3 PC PC 3 jdisp8 if A bit 1 then reset A bit X bit addr16 3 PC PC ...

Page 444: ...tions 18 MOV SEL NOP EI DI Operation Mnemonic Operand No of bytes Flags STBC byte 4 STBC byte RBn 2 RBS1 0 n n 0 3 1 No operation 1 IE 1 Enable interrupts 1 IE 0 Disable interrupts Z AC CY 14 CPU control instructions MOV SEL NOP EI DI ...

Page 445: ...ROR4 ROL4 POP PUSH MOV MOV ADDNote 1 MOV MOV MOV MOV XCH ADDNote 1 MOV XCH ADDNote 1 MOV XCH ADDNote 1 A r rl saddr sfr mem1 mem1 addr16 addr16 PSW STBC MOV 18 3 INSTRUCTION LISTS FOR EACH ADDRESSING TYPE 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC SHR SHL ROR4 ROL4 and DBNZ Table 18 1 8 Bit Instructions for Each Addressing Type Notes 1 ADDC S...

Page 446: ... 16 Bit Instructions for Each Addressing Type First operand Second operand word AX sfr mem1 mem1 ADDW SUBW CMPW MOVW ADDW SUBW CMPW MOVW ADDW SUBW CMPW AX rp rp saddrp SP n None ADDW SUBW CMPW rp MOVW MOVW sfrp mem1 mem1 MOVW MOVW SP saddrp MOVW MOVW MOVW MOVW MOVW DECW INCW PUSH POP SHLW SHRW DECW INCW MOVW MOVW MOVW ...

Page 447: ...bit saddr bit sfr bit saddr bit sfr bit PSW bit PSW bit MOV1 AND1 OR1 XOR1 AND1 OR1 AND1 OR1 MOV1 AND1 OR1 XOR1 AND1 OR1 MOV1 AND1 OR1 XOR1 AND1 OR1 MOV1 AND1 OR1 XOR1 AND1 OR1 CLR1 NOT1 SET1 CLR1 NOT1 SET1 BF BT BTCLR MOV1 A bit CLR1 NOT1 SET1 BF BT BTCLR MOV1 X bit CLR1 NOT1 SET1 BF BT BTCLR MOV1 saddr bit CLR1 NOT1 SET1 BF BT BTCLR MOV1 sfr bit CLR1 NOT1 SET1 BF BT BTCLR MOV1 PSW bit Note The s...

Page 448: ... Table 18 4 Call Instructions and Branch Instructions for Each Addressing Type Instruction addressing operand addr16 addr16 rp addr11 addr5 BR BCNote BT BF BTCLR DBNZ Basic instruction Composite instruction MOV1 CALL BR CALL BR MOV1 Note BL BNC BNL BZ BF BNZ and BNE are the same as BC 5 Other instructions ADJBA ADJBS BRK RET RETI RETB NOP EI DI and SEL ...

Page 449: ...420 ...

Page 450: ...421 A APPENDIX A 78K II SERIES PRODUCT LIST The following pages list the 78K II series products For details refer to each User s Manual ...

Page 451: ...e I O pins Input Output I O Total With a pull up resistor LED direct drive output Transister direct drive output P0 P1 P2 P3 P4 P5 P6 P7 P6 and PM6 P6 only 14 8 12 12 20 28 10 28 35 25 10 28 54 36 54 63 45 36 54 34 16 34 None 16 34 8 None 16 0 16 8 0 16 8 bit output port 8 bit I O port 8 bit input port 8 bit I O port 8 bit I O port 8 bit I O port 8 bit I O port 8 bit I O port 8 bit I O port 8 bit ...

Page 452: ...18 36 46 64 54 36 46 64 24 42 24 42 8 8 24 8 24 8 bit output port 8 bit I O port 8 bit input port 8 bit I O port 8 bit I O port 8 bit I O port 8 bit I O port 8 bit I O port 8 bit I O port 8 bit I O port 4 bit output port 4 bit I O port 4 bit output port 2 bit I O port 4 bit output port 4 bit I O port 4 bit output port 2 bit I O port 4 bit output port 4 bit I O port 8 bit input port 6 bit input por...

Page 453: ... D conversion Pin voltage is 0 V to AVREF during A D conversion 3 4 V to VDD 3 6 V to VDD None D A converter 16 bit timer counter 8 bit timer counter Timer output PWM PPG output One shot pulse Interrupt source External SFR area UART CSI BRG timer Baud rate generator External baud rate clock input Real time output port 1 3 2 4 Provided None None None 7 5 16 bytes 0FFD0H to 0FFDFH None 1 channel 1 c...

Page 454: ...4 µPD78244 12 bits 2 None Selected freely Selected according to operating frequency 1 3 4 Provided Provided 7 16 bytes 0FFD0H to 0FFDFH 1 channel 1 channel SBI Provided shared with timer counter 3 3 4 V to VDD 3 6 V to VDD 8 bits 2 None Provided 4 bits 2 or 8 bits 1 Provided Pins subject to A D conversion Pin voltage is 0 V to AVREF during A D conversion ...

Page 455: ...elevant user s manual HALT STOP mode Fixed Fixed Selected from two options Provided refresh pulse width 1 fCLK None FC80H to FDFFH cannot be accessed during refresh Provided refresh pulse width 1 5 fCLK 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 14 mm 64 pin ceramic shrink DIP with window for µPD78P218A only 64 pin plastic shrink DIP 750 mil 68 pin plastic QFJ except µPD78212 64 pin p...

Page 456: ...Refer to the relevant user s manual HALT STOP mode Selected from two options Provided refresh pulse width 1 fCLK None MODE pin high level cannot be set 84 pin plastic QFJ 80 pin plastic QFP 14 14 mm 94 pin plastic QFP 20 20 mm 94 pin ceramic WQFN for µPD78P238 only 64 pin plastic shrink DIP 750 mil 64 pin plastic QFP 14 14 mm µPD78234 µPD78244 12 14 Increments 16 bits EA pin low level MODE pin hig...

Page 457: ...428 ...

Page 458: ...429 B APPENDIX B DEVELOPMENT TOOLS The development tools described on the following pages are available for the development of systems using µPD78214 sub series ...

Page 459: ...er PG 1500 PA 78P214CW PA 78P214GC PA 78P214GJ PA 78P214GQ PA 78P214L Product containing PROM PD78P214CW DW PD78P214GC PD78P214GJ PD78P214GQ PD78P214L PD78P214CW A PD78P214GC A µ µ µ µ User system Note 3 When the in circuit emulator is connected to the host mahine When the in circuit emulator is connected to the console so that it is used as a stand alone emulator µ µ µ DEVELOPMENT ENVIRONMENT Not...

Page 460: ...s the EP 78210CW the only difference being that the former has a longer cable These emulation probes are used for the µPD78212GC AB8 µPD78213GC AB8 µPD78214GC AB8 µPD78P214GC AB8 µPD78212GC A AB8 and µPD78214GC A AB8 Both are used together with the EV 9200GC 64 The EP 78240GC R is essentially the same product as the EP 78210GC the only difference being that the former has a longer cable This emula...

Page 461: ... with the µPD78P214CW and µPD78P214DW It is used together with a PROM programmer such as the PG 1500 This PROM programmer adapter is used with the µPD78P214GC AB8 It is used together with a PROM programmer such as the PG 1500 This PROM programmer adapter is used with the µPD78P214GJ 5BJ It is used together with a PROM programmer such as the PG 1500 This PROM programmer adapter is used with the µPD...

Page 462: ... name LCNV78K2 Converts a source program written in the structured assembler language into a form that can be input into the relocatable assembler Converts a source program written in assembly language into a machine language program enabling the genera tion of a relocatable object module file Links an object module file generated by the relocatable assembler with a library file to determine the a...

Page 463: ...HC This C compiler can be used with all 78K II series products Its language specifica tions conform to ANSI standards and compiled programs can be written into ROM The compiler offers such features as special function register manipulation bit manipulation variables using short direct addressing and interrupt control The use of these features ensures effective programming and high object efficienc...

Page 464: ...rcuit emulator has been upgraded to IE 78240 R A class and a PC 9800 series or IBM PC AT computer is being used as a host computer This debugger can debug source programs written in C structured assembly language and assembly language Its split screen function by which the screen is split into sections to enable the simultaneous display of different information makes debugging more efficient Scree...

Page 465: ...n B 2 4 MS DOS See Section B 2 4 Host machine Emulator IE 78210 R IE 78210 R EM IE 78240 R IE 78240 R EM PC 9800 series Ver 3 10 to Ver5 00ANote 2 PC 9800 series Ver 3 10 to Ver5 00ANote 2 IBM PC AT or compatible IBM PC AT or compatible Notes 1 When using the IE 78210 R or IE 78210 R EM the IE 78210 is also necessary For the IE 78240 R or IE 78240 R EM the IE 78240 is necessary When using the IE 7...

Page 466: ... 00A feature a task swap function However the task swap function cannot be used with this software 2 The 5 25 inch 2D model is no longer available Those users who have already purchased a 5 25 inch 2D model will be supplied with a 5 25 inch 2HC model when the product is next upgraded B 2 4 OS for the IBM PC The following OSs are supported for the IBM PC PC DOS WindowsNote 1 MS DOS IBM DOS OS Ver 3...

Page 467: ...red Board The high speed download function is not supported Those users who are also using an in circuit emulator of IE group 1 2 or 4 are recommended to upgrade these emulators also Those users with an in circuit emulator of IE group 1 do not need to purchase the IE 78200 R BK the IE 78200 R BK board is built into the IE group 1 in circuit emulator Those users with an in circuit emulator of IE gr...

Page 468: ... to purchase the IE 78200 R EM the IE 78200 R EM board is built into the IE group 1 in circuit emulator Remarks B 3 2 Upgrading to IE 78240 R LevelNote 1 Upgrading to IE 78240 R A Level is recommended 4 5 IE 78240 R EM 2 3 IE 78200 R EMNote 1 IE 78240 R EM IE 78200 R EMNote 1 IE 78240 R EMNote 2 IE 78200 R EMNote 1 IE 78240 R EM Those users who have an in circuit emulator of IE group 1 do not need...

Page 469: ...0 R EM board is built into the IE group 1 in circuit emulator Remarks IE 78210 R EMNote 1 1 B 3 3 Upgrading to IE 78210 R LevelNote 2 Upgrading to IE 78240 R A level is recommended 2 IE 78200 R EMNote 2 IE 78210 R EMNote 1 3 Upgrading to IE 78210 R level is not allowed Upgrading to IE 78240 R or IE 78240 R A is recommended Notes 1 This board is no longer produced and is not available from NEC Thos...

Page 470: ...ool OS µS5A10FI78K2 µS5A13FI78K2 µS7B10FI78K2 µS7B13FI78K2 Part number 5 25 inch 2HD 3 5 inch 2HD 5 25 inch 2HC 3 5 inch 2HC Distribution medium PC 9800 series Host machine See Section B 2 4 This program is used to evaluate and adjust fuzzy knowledge data at the hardware level using the in circuit emulator Fuzzy inference debugger FD78K II OS µS5A10FD78K2 µS5A13FD78K2 µS7B10FD78K2 µS7B13FD78K2 Par...

Page 471: ...442 ...

Page 472: ...synchronous serial interface mode register ASIM 245 Asynchronous serial interface status register ASIS 246 B Baud rate generator control register BRGC 251 C Capture compare control register 0 CRC0 112 Capture compare control register 1 CRC1 144 Capture compare control register 2 CRC2 165 Clock synchronous serial interface mode register CSIM 262 273 E External interrupt mode register 0 INTM0 294 Ex...

Page 473: ...M1 143 164 Priority specification flag register PR0 306 Programmable wait control register PW 347 Pull up resistor option register PUO 65 74 78 82 91 R Real time output port control register RTPC 97 Refresh mode register RFM 367 S Serial bus interface control register SBIC 264 Serial reception buffer RXB 245 Serial shift register SIO 276 Serial transmission shift register TXS 245 Standby control r...

Page 474: ...compare register 161 CR22 8 bit capture register 161 CR30 8 bit compare register 206 CRC0 Capture compare control register 0 112 CRC1 Capture compare control register 1 144 CRC2 Capture compare control register 2 165 CSIM Clock synchronous serial interface mode register 262 273 I IF0 Interrupt request flag register 305 INTM0 External interrupt mode register 0 294 INTM1 External interrupt mode regi...

Page 475: ...5 74 78 82 91 PW Programmable wait control register 347 R RFM Refresh mode register 367 RTPC Real time output port control register 97 RXB Serial reception buffer 245 S SBIC Serial bus interface control register 264 SIO Serial shift register 276 STBC Standby control register 379 T TM0 16 bit timer 0 111 TM1 8 bit timer 1 142 TM2 8 bit timer 2 161 TM3 8 bit timer 3 206 TMC0 Timer control register 0...

Page 476: ...serial interface operations 247 Asynchronous serial interface status register 246 Automatic addition 331 Auxiliary carry flag 46 B Bank register 43 Basic operation 121 Baud rate 251 254 Baud rate generator 243 251 Baud rate generator control register 251 Baud rate generator for UART 243 Baud rate setting 254 Both edges 294 Both edge detector 251 Buffer register 97 Built in pull up resistor 59 65 7...

Page 477: ... function 170 External event counter operation mode 170 External extension data memory 43 External interrupt mode register 293 294 External memory 43 External memory expansion mode 346 External SFR area 43 External trigger 118 149 177 F Framing error 249 Frequency divider 251 253 Full count 175 Full duplex transmission 243 G General purpose register 47 H Hardware start 225 235 I I O circuit 33 I O...

Page 478: ...xpansion mode register 76 80 346 Memory map 38 Memory space 37 Minimum interval 109 139 159 205 Minimum pulse width 109 160 161 Modulo register 334 Multiple interrupt 307 313 Multiple interrupt handling 306 Multiplexed address data bus 345 Multiplexed analog 225 N Noise elimination 296 Noise eliminator 389 Nonmaskable interrupt 308 Nonmaskable interrupt request 303 307 Number of I O ports 60 Numbe...

Page 479: ...9 265 Reception 249 267 Reception buffer 245 Reception control parity check 245 Reception error 246 249 Reference voltage pin 227 Refresh bus cycle 367 Refresh function 367 Refresh mode register 367 Refresh pulse 367 Register bank selection flag 46 Register 45 Release detection flag 274 Release trigger bit 274 Releasing the busy state 287 Reset 389 Reset function 389 Reset vector table 389 Resolut...

Page 480: ...ister 0 111 207 Timer control register 1 143 163 Timer macro service pointer 334 Timer output mode 112 165 Timer output control register 113 119 166 179 Timer output 119 179 Timer counter unit 107 Timing in three wire serial I O mode 266 Transmission 248 267 Transmission and reception 267 Transmission control parity generation 245 Transmission data 248 265 Transmission shift register 245 Trigger i...

Page 481: ...ersion 234 A D conversion result 230 231 235 A D conversion result register 225 A D conversion start signal 295 A D converter 225 A D converter mode register 228 ADCR 225 227 ADM 228 304 ALV0 113 ALV1 113 ALV2 166 ALV3 166 AN0 225 AN1 225 AN2 225 AN3 225 AN4 225 AN5 225 AN6 30 225 239 AN7 30 225 239 ANI0 229 ANI1 229 ANI2 229 ASCK 28 253 258 ASIM 245 247 ASIS 246 ASTB 31 345 AVREF 31 227 AVSS 31 2...

Page 482: ... CMK00 306 CMK01 306 CMK10 306 CMK11 306 CMK20 306 CMK21 306 CPR00 307 CPR01 307 CPR10 307 CPR11 307 CPR20 307 CPR21 307 CR00 111 117 CR01 111 117 CR02 111 118 CR10 142 148 CR11 142 148 CR20 161 176 CR21 161 176 CR22 161 177 CR30 206 210 CRC0 112 119 CRC1 144 CRC2 165 179 CRXE 262 273 CS 229 304 CSIIF 305 CSIISM 306 CSIM 262 273 CSIMK 306 CSIPR 307 CTXE 262 273 CY 45 308 D D 48 D0 31 D1 31 D2 31 D...

Page 483: ...1 176 302 INTC30 210 302 INTCSI 302 Interrupt request from the A D converter 239 INTM0 293 INTM1 293 INTP0 28 99 149 294 302 INTP1 28 177 294 302 INTP2 28 161 294 302 INTP3 28 118 295 302 INTP4 28 295 302 303 INTP5 28 225 239 295 302 303 304 INTSER 249 302 INTSR 249 302 INTST 248 302 IRAM 43 ISM0 304 306 ISM0H 306 ISM0L 306 ISP 45 308 ISP flag 311 IST 304 307 L L 48 M MDL0 252 MDL1 252 MDL2 252 MD...

Page 484: ... PISM0 306 PISM1 306 PISM2 306 PISM3 306 PISM4 306 PISM5 306 PM0 61 PM3 72 PM5 81 PM6 89 PMC3 72 PMK0 306 PMK1 306 PMK2 306 PMK3 306 PMK4 306 PMK5 306 Port 0 60 Port 2 63 Port 3 66 Port 4 75 Port 5 80 Port 6 84 Port 7 92 PPG frequency 125 186 PPG output 125 185 PPG period 125 185 PPG pulse width 125 185 PPR0 307 PPR1 307 PPR2 307 PPR3 307 PPR4 307 PPR5 307 PR0 304 307 PR0H 307 PR0L 307 PRAM 43 PRM...

Page 485: ...R R0 49 R1 49 R2 49 R3 49 R4 49 R5 49 R6 49 R7 49 RBS0 46 308 RBS1 46 308 RC 334 RD 30 345 REFRQ 30 RELD 280 Releasing HALT mode 485 Releasing STOP mode 382 RELT 280 RESET 31 389 RETB 308 RETB instruction 308 RETI 308 RETI instruction 308 RFEN 367 RFLV 367 RFM 367 RFT0 367 RFT1 367 ROM less 42 RP0 49 RP1 49 RP2 49 RP3 49 RTPC 61 97 RXB 245 RxD 29 RXE 246 S SAR 227 SB0 270 SBI 272 SBIC 263 SBI mode...

Page 486: ... 379 STIF 305 STISM 306 STMK 306 STOP mode 377 382 STP 379 STPR 307 T TM0 111 114 TM1 142 145 TM2 161 167 TM3 206 208 TMC0 111 207 TMC1 143 163 TO0 29 119 TO1 29 119 TO2 29 179 TO3 29 179 TOC 113 119 166 179 TPS0 252 TPS1 252 TPS2 252 TRG 229 304 TxD 29 TXS 245 V VDD 31 VPP 31 VSS 31 32 W WAIT 30 WR 30 345 WUP 262 273 X X 48 X1 31 55 X2 31 55 Z Z 46 308 ...

Page 487: ...458 ...

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