NEC PD78212, User Manual

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Chapter 7 Timer/Counter Units
7
(1) 16-bit timer 0 (TM0)
TM0 is a count-up timer using a count clock of f
CLK
/8.
The count operation of TM0 can be enabled or disabled by timer control register 0 (TMC0).
TM0 allows only read operation using a 16-bit manipulation instruction. When the RESET signal is applied,
TM0 is cleared to 0000H, and count operation stops.
(2) Compare registers (CR00, CR01)
The CR00 and CR01 registers are 16-bit registers for holding a value that determines the period of the interval
timer.
When the values of the CR00 and CR01 registers coincide with the value of TM0, interrupt requests (INTC00,
INTC01) and timer output control signals are generated. Count value clear operation can also be performed
when the value of CR01 coincides with the value of TM0.
The compare registers allow both read and write operations using a 16-bit manipulation instruction. When
the RESET signal is applied, the compare registers become undefined.
(3) Capture register (CR02)
The CR02 register is a 16-bit register for capturing the value of TM0.
Capture operation is performed on a valid edge (capture trigger) occurring on the external interrupt request
(INTP3) input pin. The value of CR02 register is held until the next capture trigger occurs.
The CR02 register allows only read operation using a 16-bit manipulation instruction. When the RESET signal
is applied, the CR02 register becomes undefined,
(4) Edge detector
The edge detector detects a valid edge of an external input signal.
When the edge detector detects, on the INTP3 input pin, a valid edge specified in external interrupt mode
register 1 (INTM1), INTP3 and a capture trigger are generated. (See
Fig. 11-2 for information about the INTM1
register.)
(5) Output control circuit
When the value of CR00 or CR01 coincides with the value of TM0, timer output can be inverted. By setting
the lower 4 bits of the timer output control register (TOC), a square wave can be output on a timer output pin
(TO0, TO1). At this time, PWM/PPG output is possible, depending on the setting of capture/compare control
register 0 (CRC0).
Timer output can be disabled or enabled by the TOC register. When timer output is disabled, the inactive level
is output on the TO0 and TO1 pins. (The active level is set using the TOC register.)
7.1.3 16-Bit Timer/Counter Control Registers
(1) Timer control register 0 (TMC0)
The TMC0 register is an 8-bit register for controlling the count operation of 16-bit timer 0 (TM0).
The lower 4 bits control the count operation of TM0. (The higher 4 bits control the count operation of 8-bit
timer/counter 3.)
The TMC0 register allows both read and write operations using an 8-bit manipulation instruction. Fig. 7-3
shows the format of the TMC0 register.
When the RESET signal is applied, the TMC0 register is cleared to 00H.