NEC PD78212, User Manual

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343
Chapter 12 Interrupt Functions
12
12.5 NOTES
(1) Do not use the RETI instruction to return from the software interrupt.
(2) A macro service request is accepted and processed even when a nonmaskable interrupt service program is
running. To disable macro service processing during execution of the nonmaskable interrupt service
program, cause the nonmaskable interrupt service program to manipulate the mask register so that no macro
service will not occur.
(3) If the IE bit of the PSW is set to 1, for example, by executing the EI instruction in the nonmaskable interrupt
service program, maskable interrupt requests assigned high priority are made acceptable. If a maskable
interrupt with high priority occurs during execution of the nonmaskable interrupt service program, a service
program for the maskable interrupt runs. If the IE and ISP bits of the PSW are set to 1, interrupt requests with
low priority will also occur, thus causing the interrupt service program to run. An RETI instruction will be used
to return from the maskable interrupt service program. The RETI instruction resets the NMIS bit to 0, thus
enabling nonmaskable interrupt requests even when multiple-interrupt handling should not be performed for
nonmaskable interrupts during execution of the nonmaskable interrupt service program to which a return was
just made. To inhibit multiple-interrupt handling for nonmaskable interrupt requests, do not enable interrupts
during execution of the nonmaskable interrupt service program.
(4) Nonmaskable interrupts are always accepted except during execution of the nonmaskable interrupt handling
program (except when multiple-interrupt handling for nonmaskable interrupts have been enabled by
resetting the NMIS bit of the IST register to 0 during execution of the nonmaskable interrupt handling
program) and except a period between a special instruction described in
Section 12.3.5 and an instruction that
follows that special instruction. Therefore, nonmaskable interrupts are accepted, even if the contents of the
stack pointer are undefined, for example, right after a reset occurs. At this point, the contents of the PC and
PSW may be transferred to addresses (see
Table 3-4 in Section 3.2.5 ) where writing to any special-function
register is inhibited, depending on the value in the stack pointer. If this occurs, the CPU may hang, unexpected
signals may be output from pins, or an attempt may be made to transfer the contents of the PC or PSW to a
location where no RAM has been installed, thereby making it impossible to return from the nonmaskable
interrupt handling program to the main routine, hence a program crash.
If a falling edge (valid edge of the NMI input after a reset) arrives at the NMI pin at much the same time when
a rising edge is supplied to the RESET pin, a branch occurs to the nonmaskable interrupt handling program
without executing a single instruction after a reset, resulting in a program crash almost with no exception.
To avoid these problems, initialize the stack pointer after a reset, and design the hardware so that the NMI
signal does not drop within 10
µ
s + 20/f
CLK
after the RESET signal rises.
(5) When a BF instruction is used to poll registers related to interrupts, do not specify this BF instruction as the
branch destination. Otherwise, all interrupts and macro services are kept pending until a condition that
inhibits a branch is met during execution of the instruction.
Example of incorrect coding
LOOP: BF IF0H.3, $LOOP
←
× × ×
Example of correct coding (1)
LOOP: NOP
←
BF IF0H.3, $LOOP
All interrupts and macro services are kept pending, until
IF0H.3 is set to 1. The pending state continues until the
instruction next to the BF is executed.
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Interrupts or macro services will not be kept pending long,
because they are processed after the NOP is executed.