NEC PD78212, User Manual

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385
Chapter 14 Standby Function
14
Fig. 14-6 Example of Address Bus Arrangement
Power supply backed up
V
DD
V
DD
V
SS
V
SS
IN
Diode with small V
F
An
(n = 8 to 15)
Power supply not backed up
CMOS IC , etc. PD78214
µ
The outputs of the address/data bus pins are high-impedance in STOP mode. The address/data bus pins are
usually pulled up with pull-up resistors. If a pull-up resistor is connected to a power supply which is backed
up, current flows through the pull-up resistor to an external circuit that is connected to a power supply that
is not backed up, if the circuit has low input impedance. As a result, current consumption increases. To
prevent this, connect pull-up resistors to any power supply that is not backed up, as shown in Fig. 14-7.
Fig. 14-7 Example Address/Data Bus Arrangement
Power supply backed up
V
DD
V
DD
V
SS
V
SS
IN/OUT
ADn
(n = 0 to 7)
Power supply not backed up
CMOS IC , etc. PD78214
µ
The outputs of the RD, WR, ASTB, and REFRQ pins are fixed in STOP mode and, therefore, require the same
arrangements as the address bus pins. The ASTB pin, which outputs a low voltage, usually does not require
any external parts.
The level of the voltage input to the WAIT pin must be maintained between V
SS
and V
DD
. Any voltage falling
outside this range increases the current consumption as well as adversely affecting the reliability of the
microcomputer.
For the
µ
PD78214, you can prevent problems related to address/data bus pins simply by specifying port mode
for the pins. The
µ
PD78213, however, requires that the above arrangements be implemented.
(5) A/D converter
When the CS bit (bit 7) of the A/D converter mode register (ADM) is reset to 0, the current flowing from the
AV
REF
pin is reduced. To reduce the current further, cut off the current supplied to the AV
REF
pin by means
of an external circuit. In this case, however, a voltage higher than that of the AV
REF
pin must not be applied
to the following pins:
• Pin selected with bits ANI0 to ANI2 when the MS bit of the ADM register is 0
• AN0 pin when the MS bit of the ADM register is 1
Fig. 14-8 shows an example arrangement for preventing voltages higher than that of the AV
REF
pin. Note,
however, that in this case, response to changes in the input signal may become slow due to the time constant
derived from C and R on the input line.