National Instruments AT-MIO-64F-5, User Manual

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Register Map and Descriptions Chapter 4
AT-MIO-64F-5 User Manual 4-14 © National Instruments Corporation
Bit Name Description (continued)
Table 4-3. DMA and Interrupt Modes (Continued)
Interface Mode
IO_INT
DMACHA
DMACHB
ADCREQ
DAC1REQ DAC0REQ
Mode Description
1 1 0 0 0 1 Channel A to DAC0 with ADC interrupt
1 1 0 0 1 0 Channel A to DAC1 with ADC interrupt
1 1 0 0 1 1 Channel A to DAC0 and DAC1 (interleaved) with ADC interrupt
1 1 0 1 0 0 Channel A from ADC with timer interrupt
1 0 1 0 1 0 Channel B to DAC1 with ADC interrupt
1 0 1 0 1 1 Channel B to DAC0 and DAC1 (interleaved) with ADC interrupt
1 0 1 1 0 0 Channel B from ADC with timer interrupt
1 1 1 0 0 0 Channels A and B to DACs 0 and 1 (double-buffered) with ADC interrupt
1 1 1 0 0 1 Channel A and Channel B to DAC0 (double-buffered) with ADC interrupt
1 1 1 0 1 0 Channel A and Channel B to DAC1 (double-buffered) with ADC interrupt
1 1 1 0 1 1 Channels A and B to DACs 0 and 1 (sync double-channel) with ADC interrupt
1 1 1 1 0 0 Channels A and B from ADC (double-buffered) with timer interrupt
1 1 1 1 0 1 Channel A to DAC0 and Channel B from ADC
1 1 1 1 1 0 Channel A to DAC1 and Channel B from ADC
1 1 1 1 1 1 Channel A to DAC0 and DAC1 (interleaved) and Channel B from ADC
5 DAC1REQ DAC 1 Request Enable Ð This bit controls DMA requesting and interrupt
generation from D/A updates. If this bit is set, an interrupt or DMA
request is generated when the DAC is ready to receive data. If this bit is
cleared, no DMA request or interrupt is generated. To select a specific
mode, refer to Table 4-3 for available modes and associated bit patterns.
4 DAC0REQ DAC 0 Request Enable Ð This bit controls DMA requesting and interrupt
generation from D/A updates. If this bit is set, an interrupt or DMA
request is generated when the DAC is ready to receive data. If this bit is
cleared, no DMA request or interrupt is generated. To select a specific
mode, refer to Table 4-3 for available modes and associated bit patterns.
3 DRVAIS Drive Analog Input Sense Ð This signal controls the AI SENSE signal at
the I/O connector. AI SENSE is always used as an input in the NRSE
input configuration mode irrespective of DRVAIS. If DRVAIS is set ,
then AI SENSE is connected to board ground unless the board is
configured in the NRSE mode, in which case AI SENSE is used as an
input. If DRVAIS is cleared, AI SENSE is used as an input in the NRSE
input configuration, and is not driven otherwise.