National Instruments AT-MIO-64F-5, User Manual

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Theory of Operation Chapter 3
AT-MIO-64F-5 User Manual 3-4 © National Instruments Corporation
8-bit access to a 16-bit location, and vice versa, is invalid and will cause sporadic operation. The
interrupt control circuitry routes any enabled board-level interrupt requests to the selected
interrupt request line. The interrupt requests are tristate output signals that allow the
AT-MIO-64F-5 board to share the interrupt line with other devices. Eight interrupt request lines
are available for use by the AT-MIO-64F-5ÐIRQ3, IRQ4, IRQ5, IRQ7, IRQ10, IRQ11, IRQ12,
and IRQ15. These interrupt levels are selectable from one of the registers in the AT-MIO-64F-5
register set. Six different interrupts can be generated by the AT-MIO-64F-5. Each of the
following cases is individually enabled and cleared:
¥ When the ADC FIFO buffer is ready to be serviced
¥ When a data acquisition operation completes (including an OVERFLOW or OVERRUN
error)
¥ When a DMA terminal count pulse is received on DMA channel A or DMA channel B
¥ When the DAC FIFO buffer is ready to be serviced
¥ When a DAC sequence completes (including an UNDERFLOW error)
¥ When a falling edge signal is detected on the DAC update signal (internal or external)
The DMA control circuitry generates DMA requests whenever an A/D measurement is available
from the ADC FIFO and when the DAC FIFO is ready to receive more data. The DMA circuitry
supports full PC I/O channel 16-bit DMA transfers. DMA channels 5, 6, and 7 of the PC I/O
channel are available for such transfers. DMA channels 0, 1, 2, and 3 are available for 16-bit
transfers on EISA computers only, and not on PC AT and compatible computers. With the DMA
circuitry, either single-channel transfer mode or dual-channel transfer mode can be selected for
DMA transfer. These DMA channels are selectable from one of the registers in the
AT-MIO-64F-5 register set.
Analog Input and Data Acquisition Circuitry
The AT-MIO-64F-5 handles 64 channels of analog input with software-programmable
configuration and 12-bit A/D conversion. In addition, the AT-MIO-64F-5 contains data
acquisition configuration for automatic timing of multiple A/D conversions and includes
advanced options such as external triggering, gating, and clocking. Figure 3-3 shows a block
diagram of the analog input and data acquisition circuitry.