National Instruments AT-MIO-64F-5, User Manual

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Index
AT-MIO-64F-5 User Manual Index-10 © National Instruments Corporation
DMA operations, 5-30
programmed cycle waveform generation, 5-19
DAC Update Register, 4-43
DAC waveform circuitry and timing, 3-14 to 3-19.
See also waveform generation programming.
analog output waveform circuitry (illustration), 3-17
block diagram, 3-15
DACMB<3..0> bit for selecting waveform modes, 4-17
FIFO continuous cyclic waveform generation, 3-17
FIFO programmed cyclic waveform generation, 3-18
FIFO pulsed waveform generation, 3-18 to 3-19
immediate updating of DACs, 3-14 to 3-15
posted DAC update timing (illustration), 3-16
posted update mode, 3-14 to 3-15
selecting waveform modes with DACMB<3..0> bits, 4-17
waveform circuitry (illustration), 3-15
waveform timing circuitry, 3-16 to 3-17
DAC0 OUT signal, 2-14, 2-27 to 2-28, C-2
DAC0 Register, 4-33
DAC0DSP bit, 4-17
DAC0REQ bit, 4-14
DAC1 OUT signal, 2-14, 2-27 to 2-28, C-2
DAC1 Register, 4-34
DAC1DSP bit, 4-17
DAC1REQ bit, 4-14
DACCMPLINT bit, 4-12
DACCOMP bit, 4-21, 5-23, 5-26
DACFIFOEF* bit, 4-21, 5-26
DACFIFOFF* bit, 4-21, 5-30
DACFIFOHF* bit, 4-21, 5-30
DACFIFORT* signal, 3-17
DACGATE bit, 4-17
DACMB<3..0> bit, 4-17
DACs, analog output
circuitry, 3-13
immediate updating, 3-14 to 3-15
output configuration, 3-14
posted updating, 3-15
DAQ Clear Register, 4-38, 5-10, 5-30, 5-31
DAQ Start Register, 4-39
DAQCMPLINT bit, 4-12
DAQCOMP bit, 4-19, 5-31
DAQEN bit, 4-6, 5-8, 5-9
DAQPROG bit, 4-19
data acquisition programming, 5-10 to 5-26
analog input circuitry, 5-4 to 5-10
analog output circuitry, 5-18
applying a trigger, 5-15 to 5-16
channel scanning, 5-7 to 5-10
continuous channel scanning, 5-7 to 5-8
interval-channel scanning, 5-8 to 5-10
clearing analog input circuitry, 5-10
cyclic waveform generation, 5-18 to 5-19
multiple-analog input channel configurations, 5-11
programmed cycle waveform generation, 5-19 to 5-21