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Chapter 4

Register Map and Descriptions

© National Instruments Corporation

4-55

AT-MIO-64F-5 User Manual

Digital I/O Register Group

The two registers making up the Digital I/O Register Group monitor and control the
AT-MIO-64F-5 digital I/O lines.  The Digital Input Register returns the digital state of the eight
digital I/O lines.  A pattern written to the Digital Output Register is driven onto the digital I/O
lines when the digital output drivers are enabled (see the description for Command Register 2).

Bit descriptions of the two registers making up the Digital I/O Register Group are given on the
following pages.

Summary of Contents for AT-MIO-64F-5

Page 1: ...Copyright 1992 1994 National Instruments Corporation All Rights Reserved AT MIO 64F 5 User Manual Multifunction I O Board for the PC AT EISA July 1994 Edition Part Number 320487 01...

Page 2: ...ices Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741...

Page 3: ...for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY D...

Page 4: ...or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel an...

Page 5: ...address and function of each of the AT MIO 64F 5 control and status registers Chapter 5 Programming contains programming instructions for operating the circuitry on the AT MIO 64F 5 Chapter 6 Calibrat...

Page 6: ...he IBM PC AT and compatible computers and to EISA personal computers Abbreviations The following metric system prefixes are used with abbreviations for units of measure in this manual Prefix Meaning V...

Page 7: ...de LSB least significant bit MSB most significant bit NRSE nonreferenced single ended PGIA programmable gain instrumentation amplifier RSE referenced single ended RTSI Real Time System Integration SCX...

Page 8: ...ents on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manua...

Page 9: ...s for Selecting Input Ranges 2 8 Analog Output Configuration 2 9 Analog Output Reference Selection 2 9 Analog Output Polarity Selection 2 9 Digital I O Configuration 2 10 Board and RTSI Clock Configur...

Page 10: ...Analog Input Configuration 3 6 PGIA 3 6 ADC FIFO Buffer 3 7 Analog Input Calibration 3 7 Data Acquisition Timing Circuitry 3 8 Single Read Timing 3 8 Single Channel Data Acquisition Timing 3 8 Multip...

Page 11: ...Q Clear Register 4 42 DAC Update Register 4 43 DAC Clear Register 4 44 General Event Strobe Register Group 4 45 DMA Channel Clear Register 4 46 DMATCA Clear Register 4 47 DMATCB Clear Register 4 48 Ex...

Page 12: ...nter Timer 5 16 Programming the Analog Output Circuitry 5 18 Cyclic Waveform Generation 5 18 Programmed Cycle Waveform Generation 5 19 Pulsed Cyclic Waveform Generation 5 21 Waveform Generation Progra...

Page 13: ......

Page 14: ...AT MIO 64F 5 Block Diagram 3 1 Figure 3 2 PC I O Channel Interface Circuitry Block Diagram 3 3 Figure 3 3 Analog Input and Data Acquisition Circuitry Block Diagram 3 5 Figure 3 4 ADC Conversion Timin...

Page 15: ...se I O Address and Base I O Address Space 2 5 Table 2 3 Available Input Configurations for the AT MIO 64F 5 2 6 Table 2 4 Actual Range and Measurement Precision Versus Input Range Selection and Gain 2...

Page 16: ......

Page 17: ...his software adjusts the offset and gain errors to zero by means of board level calibration DACs You can store calibration DAC constants resulting from the calibration procedure in the onboard EEPROM...

Page 18: ...sis data logging and chromatography The two analog output channels are useful for machine and process control analog function generation 12 bit resolution voltage source and programmable signal attenu...

Page 19: ...ou can switch between platforms with minimal modifications to your code NI DAQ comes with language interfaces for Professional BASIC Turbo Pascal Turbo C Turbo C Borland C and Microsoft C for DOS and...

Page 20: ...I signal conditioning modules SCXI 1100 32 channel differential multiplexer amplifier SCXI 1120 8 channel isolated analog input SCXI 1121 4 channel isolated transducer amplifier with excitation SCXI 1...

Page 21: ...SSR Series mounting rack and 1 0 m cable 8 channel with SC 205X cable 776336 10 776336 01 776336 11 776336 02 776336 12 776358 90 776358 92 776358 192 776579 90 776290 18 Custom Cables The AT MIO 64F...

Page 22: ...ack Consult the specification for the rack you intend to use for the location of any polarizing key The recommended manufacturer part numbers for this polarizing key are as follows Electronic Products...

Page 23: ...figure the base address selection for the AT bus interface The remaining resource selections such as DMA and interrupt channel selections are determined by programming the individual registers in the...

Page 24: ...nfiguration and Installation Chapter 2 AT MIO 64F 5 User Manual 2 2 National Instruments Corporation Figure 2 1 AT MIO 64F 5 Parts Locator Diagram This art not available in PDF version of this documen...

Page 25: ...itten to or read from as bytes or words Each register in the register set is mapped to a certain offset from the base address selection of the board as read or write and as a word or byte location as...

Page 26: ...tware packages you use with the AT MIO 64F 5 Table 2 1 lists the default settings of other National Instruments products for the PC Table 2 2 lists the possible switch settings the corresponding base...

Page 27: ...that must be set manually before the board is placed into the PC The interrupt level and DMA channels used by the AT MIO 64F 5 are selected via registers in the AT MIO 64F 5 register set The AT MIO 6...

Page 28: ...ree input configurations are described in Table 2 3 Table 2 3 Available Input Configurations for the AT MIO 64F 5 Configuration Description DIFF Differential configuration has up to 32 differential in...

Page 29: ...ces See the Types of Signal Sources section later in this chapter for more information With this input configuration the AT MIO 64F 5 can monitor up to 64 different analog input signals This configura...

Page 30: ...olar input means that the input voltage range is between Vref 2 and Vref 2 The AT MIO 64F 5 has a unipolar input range of 10 V and a bipolar input range of 10 V 5 V Polarity and range settings are pro...

Page 31: ...tput voltage at the I O connector The analog output circuitry is configurable through programming of a register in the board register set The reference and range for the analog output circuitry can be...

Page 32: ...I bus clock signal and the other boards can receive this signal or disconnect from it Many functions performed by the AT MIO 64F 5 board require a frequency timebase to generate the necessary timing s...

Page 33: ...des specifications and connection instructions for the signals given on the AT MIO 64F 5 I O connector The I O connector contains 100 pins that can be split into two standard 50 pin connectors via a c...

Page 34: ...ACH43 ACH20 ACH44 ACH21 ACH45 ACH22 ACH46 ACH23 ACH47 ACH24 ACH48 ACH25 ACH49 ACH26 ACH50 ACH27 ACH51 AISENSE AIGND ACH28 ACH52 ACH29 ACH53 ACH30 ACH54 ACH31 ACH55 ACH32 ACH56 ACH33 ACH57 ACH34 ACH58...

Page 35: ...33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 FOUT GATE5 OUT2 EXTTMRTRIG GATE1 EXTCONV EXTTRIG SCANCLK 5 V BDIO3 BDIO2 BDIO1 BDIO0 DIG GND EXTREF DAC0 OUT ACH...

Page 36: ...iguration and the first 16 channels in the single ended configuration 19 AI SENSE AI GND Analog Input Sense This pin serves as the reference node when the board is in NRSE configuration If desired thi...

Page 37: ...External Trigger In posttrigger data acquisition sequences a high to low edge on EXTTRIG initiates the sequence In pretrigger applications the first high to low edge of EXTTRIG initiates pretrigger c...

Page 38: ...hem in the posted update mode EXTTMRTRIG will also generate a timed interrupt if enabled 45 GATE2 DIG GND GATE2 This pin is from the Am9513A Counter 2 signal 46 OUT2 DIG GND OUTPUT2 This pin is from t...

Page 39: ...2 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ACH63 ACH62 ACH61 ACH60 ACH59 ACH58 ACH57 ACH56 ACH55 ACH54 ACH53 ACH52 AI GND ACH51 A...

Page 40: ...9 and ACH 52 63 63 AI GND 52 through In the DIFF mode ACH 28 39 and ACH 52 63 represent differential Channels 28 through 39 In the RSE and NRSE modes ACH 28 39 represent Channels 28 through 39 and ACH...

Page 41: ...eding the differential and common mode input ranges results in distorted input signals Exceeding the maximum input voltage rating can result in damage to the AT MIO 64F 5 board and to the PC National...

Page 42: ...isolation amplifiers An instrument or device that provides an isolated output falls into the floating signal source category The ground reference of a floating signal must be tied to the AT MIO 64F 5...

Page 43: ...he PGIA and its reference signal or return is tied to the negative input of the PGIA When the AT MIO 64F 5 is configured for differential input each signal uses two multiplexer inputs one for the sign...

Page 44: ...uration instructions are included in Chapter 4 Register Map and Descriptions AT MIO 64F 5 Board in the DIFF Input Configuration Ground Referenced Signal Source Common Mode Noise Ground Potential and s...

Page 45: ...0 63 Figure 2 8 Differential Input Connections for Nonreferenced Signals Figure 2 8 shows two bias resistors connected in parallel with the signal leads of a floating signal source If the source is tr...

Page 46: ...ias current typically 100 kW to 1 MW If the source has high output impedance you should balance the signal path as described above using the same value resistor on both the positive and negative input...

Page 47: ...gnal reference Channels 0 and 8 are the quietest and Channels 7 and 15 are the noisiest AI GND is on pins 1 and 2 which are very close to pins 3 and 4 which are Channels 0 and 1 On the other hand Chan...

Page 48: ...appears as an error in the measured voltage Figure 2 10 shows how to connect a grounded signal source to an AT MIO 64F 5 board configured for nonreferenced single ended input The AT MIO 64F 5 analog...

Page 49: ...Pins 20 through 23 of the MIO subconnector are analog output signal pins Pins 20 and 21 of the MIO subconnector are the DAC0 OUT and DAC1 OUT signal pins DAC0 OUT is the voltage output signal for anal...

Page 50: ...nnector are digital I O signal pins Pins 25 27 29 and 31 are connected to the digital lines ADIO 0 3 for digital I O port A Pins 26 28 30 and 32 are connected to the digital lines BDIO 0 3 for digital...

Page 51: ...over 50 LS TTL loads Figure 2 12 depicts signal connections for three typical digital I O applications LED 5 V TTL Signal 5 V Port A ADIO 3 0 Port B BDIO 3 0 31 29 27 25 32 30 28 26 24 DIG GND Switch...

Page 52: ...gh 50 carry general purpose timing signals and analog output provided by the onboard Am9513A Counter Timer These signals are explained in the General Purpose Timing Signal Connections section later in...

Page 53: ...resistor EXTCONV is also driven by the output of Counter 3 of the Am9513A Counter Timer This counter is also referred to as the sample interval counter The output of Counter 3 and the RTSI connection...

Page 54: ...ugh a 10 kW resistor The EXTTRIG signal is logically ANDed with the internal DAQSTART signal If a data acquisition sequence is to be initiated with an internal trigger EXTTRIG must be high at both the...

Page 55: ...apse and frequency measurements For these applications SOURCE and GATE signals can be directly applied to the counters from the I O connector The counters are programmed for various operations The Am9...

Page 56: ...applied to the counter GATE input to start the counter The counter can be programmed to start counting after receiving either a high to low edge or a low to high edge If the counter is programmed to c...

Page 57: ...y tied from the Am9513A input and output pins to the I O connector In addition the GATE SOURCE and OUT1 pins are pulled up to 5 V through a 4 7 kW resistor The input and output ratings and timing spec...

Page 58: ...d and referenced to the falling edge of the source signal applies to the case in which the counter is programmed to count falling edges The signal applied at a SOURCE input can be used as a clock sour...

Page 59: ...r within 300 nsec after the source signal rising or falling edge Field Wiring Considerations Accuracy of measurements made with the AT MIO 64F 5 can be seriously affected by environmental noise if pro...

Page 60: ...e CB 100 is useful for prototyping an application or in situations where AT MIO 64F 5 interconnections are frequently changed When you develop a final field wiring scheme however you may want to devel...

Page 61: ...board I O Connector Mux Mode Selection Switches ADC FIFO PGIA 16 Bit Sampling A D Conversion Analog Muxes V oltage Ref Ground REF 3 Data Acquisition Conversion Control 5 Channel Counter Timer Digital...

Page 62: ...O circuitry RTSI bus interface circuitry The internal data and control buses interconnect the components The theory of operation of each of these components is explained in the remainder of this chap...

Page 63: ...the board address Therefore the board address range is 000 to 3FF hex SA5 through SA9 are used to generate the board enable signal SA0 through SA4 are used to select individual onboard registers The...

Page 64: ...ced When a DAC sequence completes including an UNDERFLOW error When a falling edge signal is detected on the DAC update signal internal or external The DMA control circuitry generates DMA requests whe...

Page 65: ...MWR CONV A V AIL A D Data ADC FIFO and Sign Extension Mux Mode Selection Switches MUX0OUT MUX 0 MUX 1 MUX1OUT EXTCONV PC I O Channel EXTTRIG In Off Out Off 2 Gain PGIA GAIN1 GAIN0 CHANSEL5 CHANSEL 4 0...

Page 66: ...n the range of 10 to 10 V for bipolar operation and 0 to 10 V for unipolar operation Bipolar or unipolar mode configuration is programmed on a per channel basis and is controlled through one of the re...

Page 67: ...512 A D conversion values before any information is lost thus software or DMA has extra time 512 times the sample interval to catch up with the hardware If more than 512 values are stored in the FIFO...

Page 68: ...if a sequence of conversions is needed this method is not very reliable because it relies on the software to generate the conversions in the case of the strobe register If finely timed conversions ar...

Page 69: ...to 65 535 or 32 bit for counts up to 232 1 If a 16 bit counter is needed Counter 4 of the Am9513A Counter Timer is used If more than 16 bits are needed Counter 4 is concatenated with Counter 5 of the...

Page 70: ...s The only difference between pretrigger and posttrigger sequences for all data acquisition modes is that the sample counter waits for a gating signal in the pretrigger mode before beginning the count...

Page 71: ...les through the configuration memory without any delays between cycles Scanning is similar to the single channel acquisition in the programming of both the sample interval counter and the sample count...

Page 72: ...interval after the trigger Scanning stops at the end of the first scan sequence or at the end of the entire scan list The sequence restarts after a rising edge on Counter 2 is detected The interval sc...

Page 73: ...a coding circuitry The DAC in each analog output channel generates a voltage proportional to the input voltage reference Vref multiplied by the digital code loaded into the DAC Each DAC can be loaded...

Page 74: ...ircuitry of the AT MIO 64F 5 This circuitry uses a stable internal 5 VDC reference that is measured at the factory against a higher accuracy reference then its value is permanently stored in the EEPRO...

Page 75: ...gister in the AT MIO 64F 5 register set The DAC FIFO and RTSI latch are used for posted updating of the DACs Data written to the DACs is buffered by the DAC FIFO to be updated at a later time The DAC...

Page 76: ...so values are written to a buffer where they are updated later with a precisely timed update signal Figure 3 11 depicts the timing for the posted DAC update mode Update Trigger TMRREQ DAC Write X Y Z...

Page 77: ...moving a large demand on the PC bus bandwidth Maximum updating performance is achieved in this mode because it does not rely on the speed of the computer All described waveform modes involving cycling...

Page 78: ...y when the entire buffer fits within the DAC FIFO Figure 3 14 shows the operation of this mode COUNTER 1 2 or 5 5 4 3 2 1 0 5 DACFIFORT Figure 3 14 FIFO Programmed Cyclic Waveform Timing In this case...

Page 79: ...DIO 3 0 and BDIO 3 0 on the I O connector Figure 3 16 shows a block diagram of the digital I O circuitry I O Connector A Digital Input Register B DOUT0 Digital Output Register DOUT1 Digital Output Reg...

Page 80: ...ines act as high impedance inputs The external strobe signal EXTSTROBE shown in Figure 3 16 is a general purpose strobe signal Writing to an address location on the AT MIO 64F 5 board generates an act...

Page 81: ...re 5 MHz 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz The 16 bit counters in the Am9513A can be diagrammed as shown in Figure 3 18 SOURCE GATE OUT COUNTER Figure 3 18 Counter Block Diagram Each counter has a...

Page 82: ...conversion speed The Am9513A SOURCE5 pin is connected to the AT MIO 64F 5 RTSI switch which means that a signal from the RTSI trigger bus can be used as a counting source for the Am9513A counters The...

Page 83: ...eries boards with RTSI bus connectors can be wired together inside the PC and share these signals A block diagram of the RTSI bus interface circuitry is shown in Figure 3 19 Drivers Drivers RTSI Bus C...

Page 84: ...r any AT Series board sharing the RTSI bus The RTSI switch is programmed via its chip select and data inputs On the AT MIO 64F 5 board nine signals are connected to pins A 6 0 of the RTSI switch with...

Page 85: ...ster in bits The actual register address is obtained by adding the appropriate register offset to the I O base address of the AT MIO 64F 5 Registers are grouped in the table by function Each register...

Page 86: ...nd write 16 bit Am9513A Command Register 16 Write only 16 bit Am9513A Status Register 16 Read only 16 bit Digital I O Register Group Digital Input Register 1C Read only 16 bit Digital Output Register...

Page 87: ...ight bit 0 A square is used to represent each bit Each bit is labeled with a name inside its square An asterisk after the bit name indicates that the bit is inverted negative logic In many of the regi...

Page 88: ...up allow general control and monitoring of the AT MIO 64F 5 hardware Command Registers 1 2 3 and 4 contain bits that control operation of several different pieces of the AT MIO 64F 5 hardware Status R...

Page 89: ...high SCLK should first be pulsed high to initialize the EEPROM circuitry 14 SDATA Serial Data This bit is used to transmit a single bit of data to the EEPROM and both of the calibration DACs 13 SCLK S...

Page 90: ...n If SCANEN is set and DAQEN is also set alternate analog input channels are sampled during data acquisition under control of the channel configuration memory If SCANEN is cleared and DAQEN is set a s...

Page 91: ...is set then triggering of the data acquisition sequence by another National Instruments board over the RTSI bus is enabled Otherwise if RTSITRIG is cleared the data acquisition sequence is triggered...

Page 92: ...rigger signal The TMRTRIG signal updates the DACs in delayed update mode If A4RCV is set pin A4 of the RTSI switch drives the TMRTRIG signal If A4RCV is cleared the TMRTRIG signal is driven by the EXT...

Page 93: ...nal Reference for DAC 1 This bit controls the reference selection for DAC 1 in the analog output section If this bit is set the reference used for DAC 1 is the external reference voltage from the I O...

Page 94: ...rimary DMA Channel Selected A DMACHBB2 DMACHBB1 DMACHBB0 Secondary DMA Channel Selected B 0 0 0 DMA Channel 0 0 0 0 DMA Channel 0 0 0 1 DMA Channel 1 0 0 1 DMA Channel 1 0 1 0 DMA Channel 2 0 1 0 DMA...

Page 95: ...en the serial link is enabled Data from channels that have been marked in the channel configuration memory will be transmitted over the RTSI bus If ADCDSP is cleared the serial RTSI link is disabled i...

Page 96: ...an interrupt request is generated when the data acquisition operation completes The interrupt request is serviced by strobing the DAQ Clear Register When DAQCMPLINT is cleared completion of a data ac...

Page 97: ...l A to DAC0 and DAC1 interleaved 0 1 0 1 0 0 Channel A from ADC 0 0 1 0 0 1 Channel B to DAC0 0 0 1 0 1 0 Channel B to DAC1 0 0 1 0 1 1 Channel B to DAC0 and DAC1 interleaved 0 0 1 1 0 0 Channel B fro...

Page 98: ...1 1 1 0 Channel A to DAC1 and Channel B from ADC 1 1 1 1 1 1 Channel A to DAC0 and DAC1 interleaved and Channel B from ADC 5 DAC1REQ DAC 1 Request Enable This bit controls DMA requesting and interrup...

Page 99: ...HB 2 0 Interrupt Channel Select These bits select the interrupt channel available for use by the AT MIO 64F 5 See Table 4 4 Table 4 4 Interrupt Level Selection Bit Pattern Effect INTCHB2 INTCHB1 INTCH...

Page 100: ...Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 CLKMODEB1 CLMODEB0 DAC1DSP DAC0DSP DACMB3 DACMB2 DACMB1 DACMB0 MSB 7 6 5 4 3 2 1 0 DACGATE DB_DIS CYCLICSTOP ADCFIFOREQ SRC3SEL GATE2SEL...

Page 101: ...FIFO per update If DACMB3 is set the circuitry will determine whether to perform one read or two reads from the DAC FIFO depending on the data in the FIFO See Table 4 6 for available modes and bit pa...

Page 102: ...removed when the ADC FIFO is empty 3 SRC3SEL Source 3 Select This bit is used to configure the signal connected to Source 3 of the Am9513 Counter Timer If SRC3SEL is set Source 3 is connected to the D...

Page 103: ...rror condition If DAQCOMP is set and neither OVERFLOW nor OVERRUN is set the data acquisition operation has completed without error When DAQCOMP is set and ADCREQ in Command Register 3 is also set ena...

Page 104: ...un OVERFLOW is an error condition that occurs if the FIFO fills up with A D conversion data and A D conversions continue If OVERFLOW is set A D conversion data has been lost because of FIFO overflow I...

Page 105: ...is not half full of data If the appropriate DAC and I O modes are enabled interrupts or DMA requests are generated when the DAC FIFO is less than half full 3 DACFIFOEF DAC FIFO Empty Flag This bit ref...

Page 106: ...only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 X X X X X X X X MSB 7 6 5 4 3 2 1 0 X X X X X X X ADC_BUSY LSB Bit Name Description 15 1 X Don t care bits 0 ADC_BUSY ADC_BUSY This bit indicates th...

Page 107: ...FIFO Reading from the ADC FIFO Register location transfers data from the AT MIO 64F 5 ADC FIFO buffer to the PC Writing to the CONFIGMEM Register location sets up channel configuration information for...

Page 108: ...umbers The binary format used is determined by the mode in which the ADC is configured The bit pattern returned for either format is given as follows Address Base address 00 hex Type Read only Word Si...

Page 109: ...V 4 095 FFFF To convert from the ADC FIFO value to the input voltage measured use the following formula V ADC reading 10 V 4 096 Gain Table 4 8 Two s Complement Mode A D Conversion Values A D Conversi...

Page 110: ...2 1 0 CHANSEL1 CHANSEL0 CH_GAIN2 CH_GAIN1 CH_GAIN0 CHAN_LAST CHAN_GHOST CHAN_DSP LSB Bit Name Description 15 CHAN_SE Channel Single Ended This bit configures the analog input section for single ended...

Page 111: ...REF5V AI GND XXX110 DAC 0 OUT REF5V XXX111 DAC 1 OUT REF5V 12 CHAN_BIP Channel Bipolar This bit configures the ADC for unipolar or bipolar mode When CHAN_BIP is clear the ADC is configured for unipola...

Page 112: ...and 8 1 and 9 2 and 10 3 and 11 4 and 12 5 and 13 6 and 14 7 and 15 5 3 CH_GAIN 2 0 Channel Gain Select These three bits control the gain setting of the input PGIA for the selected channel The follow...

Page 113: ...D Register Writing to the CONFIGMEM Register following a CONFIGMEMCLR automatically sequences into the memory list for multiple channel configuration values Writing can continue until the end of the c...

Page 114: ...011010 26 26 50 011011 27 27 51 011100 28 28 52 011101 29 29 53 011110 30 30 54 011111 31 31 55 100000 32 32 56 100001 33 33 57 100010 34 34 58 100011 35 35 59 100100 36 36 60 100101 37 37 61 100110...

Page 115: ...used The output voltage generated from the digital code depends on the configuration unipolar or bipolar of the associated analog output channel This configuration is determined by control bits in th...

Page 116: ...g formula is a decimal value ranging from 2 048 to 2 047 Table 4 11 Analog Output Voltage Versus Digital Code Bipolar Mode Digital Code Voltage Output Decimal Hex Reference 10 V 2 048 F800 10 V 2 047...

Page 117: ...cess to the DAC Update Register or a timer trigger is received in one of the prescribed paths Address Base address 10 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 118: ...cess to the DAC Update Register or a timer trigger is received in one of the prescribed paths Address Base address 12 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 119: ...er Group The ADC Event Strobe Register Group consists of five registers that when written to cause the occurrence of certain events on the AT MIO 64F 5 board such as clearing flags and starting A D co...

Page 120: ...1B hex Type Read only Word Size 8 bit Bit map Not applicable no bits used Strobe Effect Clears the channel configuration memory Before the channel configuration memory is written to it must be cleared...

Page 121: ...onfiguration value to the analog input circuitry After the final write to the channel configuration memory accessing the CONFIGMEMLD Register loads the first channel configuration value Writing to the...

Page 122: ...data acquisition operation in progress empties the ADC FIFO clears the OVERRUN bit in Status Register 1 clears the OVERFLOW bit in Status Register 1 clears the DAQCOMP bit in Status Register 1 clears...

Page 123: ...ble no bits used Strobe Effect Initiates a programmed data acquisition sequence Note Multiple A D conversion data acquisition operations can be initiated in one of three ways by accessing the Start DA...

Page 124: ...no bits used Strobe Effect Initiates a single ADC conversion Note A D conversions can be initiated in one of two ways by accessing the Single Conversion Register or by applying an active low signal on...

Page 125: ...oup The DAC Event Strobe Register Group consists of three registers that when written to cause the occurrence of certain events on the AT MIO 64F 5 board such as clearing flags and updating the analog...

Page 126: ...ter 1 and its associated interrupt The analog output DACs can be updated internally and externally in the waveform generation mode through the control of A4RCV If A4RCV is enabled internal updating is...

Page 127: ...DAC0 and DAC1 simultaneously with the previously written values and removes DAC FIFO data for DAC0 DAC1 or both as programmed Address Base address 18 hex Type Write only Word Size 16 bit Bit Map Not a...

Page 128: ...ter clears parts of the DAC circuitry including emptying the DAC FIFO Address Base address 1E hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Empties the DAC FIFO...

Page 129: ...Group The General Event Strobe Register Group consists of five registers that when written to cause the occurrence of certain events on the AT MIO 64F 5 board such as clearing flags and starting A D...

Page 130: ...nel DMA When the first DMA channel terminal count is reached the circuitry automatically sequences the second DMA channel When the second DMA channel terminal count is reached the circuitry returns to...

Page 131: ...rated from the Channel A terminal counter interrupt When the selected DMA channel A reaches its terminal count the DMATCA signal in the Status Register is asserted If DMATC interrupts are enabled an i...

Page 132: ...d from the Channel B terminal counter interrupt When the selected DMA channel B terminal count is reached the DMATCB signal in Status Register 1 is asserted If DMATC interrupts are enabled an interrup...

Page 133: ...y MIO connector This signal has a minimum low time of 500 nsec The EXTSTROBE pulse is useful for several applications including generating external general purpose triggers and latching data into exte...

Page 134: ...tion DAC 0 Load Register Accessing the Calibration DAC 0 Load Register loads the serial data previously shifted into one of the eight selected 8 bit calibration DACs Address Base address 0A hex Type W...

Page 135: ...as general purpose timing for the user The Am9513A registers described here are the Am9513A Data Register the Am9513A Command Register and the Am9513A Status Register The Am9513A contains 18 addition...

Page 136: ...ers for Counters 1 2 3 4 and 5 Counter Hold Registers for Counters 1 2 3 4 and 5 The Master Mode Register The Compare Registers for Counters 1 and 2 All these registers are 16 bit registers Bit descri...

Page 137: ...sed through the Am9513A Data Register Address Base address 16 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 C7 C6 C5 C4C C3 C2 C1 C0 MSB LSB Bit Na...

Page 138: ...0 9 8 X X X X X X X X MSB 7 6 5 4 3 2 1 0 X X OUT5 OUT4 OUT3 OUT2 OUT1 BYTEPTR LSB Bit Name Description 15 6 X Don t care bits 5 1 OUT 5 1 Each of these five bits returns the logic state of the associ...

Page 139: ...ol the AT MIO 64F 5 digital I O lines The Digital Input Register returns the digital state of the eight digital I O lines A pattern written to the Digital Output Register is driven onto the digital I...

Page 140: ...5 digital I O lines Address Base address 1C hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 X X X X X X X X MSB 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIO1 BDIO0 ADIO3 ADIO2 ADIO1 ADIO0 LSB Bi...

Page 141: ...ort Address Base address 1C hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 MSB 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIO1 BDIO0 ADIO3 ADIO2 ADIO1 ADIO0 LSB Bit Name Descript...

Page 142: ...m several AT MIO 64F 5 signal lines The RTSI switch is programmed by shifting a 56 bit routing pattern into the RTSI switch and then loading the internal RTSI Switch Control Register The routing patte...

Page 143: ...is a 1 bit register and must be written to 56 times to shift the 56 bits into the internal register Address Base address 0C hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RS...

Page 144: ...to in order to load the contents of the RTSI Switch Shift Register into the RTSI Switch Control Register thereby updating the RTSI switch routing pattern The RTSI Switch Strobe Register is written to...

Page 145: ...erefore you should maintain a software copy of the write only registers This software copy can then be read to determine the status of the write only registers To change the state of a single bit with...

Page 146: ...AT MIO 64F 5 circuitry in the following state DMA and interrupts are disabled The DMA circuitry is cleared The outputs of counter timers are in the high impedance state The analog input circuitry is i...

Page 147: ...o theAm9513A Data Register Write 0xFF08 ctr to the Am9513ACommand Register Write 0x0003 to theAm9513A Data Register Write 0xFF5F to theAm9513A Command Register ctr 1 ctr 6 END START No Y es Issue a ma...

Page 148: ...els are scanned in a round robin fashion separated in time by the programmed sample interval The final mode is the interval scanning mode This mode should be used if more than one channel needs to be...

Page 149: ...es whether one or more A D conversion results are stored in the ADC FIFO If the ADCFIFOEF bit is not set the ADC FIFO is empty and reading the ADC FIFO Register returns meaningless data After an A D c...

Page 150: ...ming multiple A D conversions on a single channel requires the following programming steps for posttrigger and pretrigger modes as well as internal and external timing The instructions in the blocks o...

Page 151: ...the data acquisition There is no delay between the cycles of the scan sequence Continuous channel scanning can be thought of as a round robin approach to scanning multiple channels Interval channel sc...

Page 152: ...nction with the DAQEN bit in Command Register 1 enables scanning during multiple A D conversions The SCANEN bit must be set regardless of the type of scanning used continuous or interval otherwise onl...

Page 153: ...interval scanning data acquisition operation Apply a trigger Service the data acquisition operation Program the scan interval counter Figure 5 5 Interval Scanning Data Acquisition Programming Setting...

Page 154: ...RFLOW and OVERRUN are cleared Pending data acquisition interrupt requests are cleared ADC FIFO is emptied DAQCOMP flag in the Status Register is cleared Empty the ADC FIFO before starting any A D conv...

Page 155: ...data acquisition begins To load the channel configuration memory perform the following write operations where N is the number of entries in the scan sequence Strobe the CONFIGMEMCLR Register For i 0 t...

Page 156: ...ad value 5 Write FF44 to the Am9513A Command Register to load Counter 3 6 Write FFF3 to the Am9513A Command Register to step Counter 3 down to 1 7 Write the desired sample interval to the Am9513A Data...

Page 157: ...r to load Counter 4 6 Write FFF4 to the Am9513A Command Register to decrement Counter 4 7 Write FF28 to the Am9513A Command Register to arm Counter 4 8 Clear the CNT32 16 bit in Command Register 1 to...

Page 158: ...13A Command Register to load and arm Counter 5 13 Set the CNT32 16 bit in Command Register 1 to notify the hardware that both Counters 4 and 5 will be used as the sample counter After you complete thi...

Page 159: ...sequence Write the desired scan interval to the Am9513A Data Register to store the Counter 2 load value If the scan interval is between 2 and FFFF 65 535 decimal write the scan interval to the Am9513A...

Page 160: ...cquisition has completed 1 Read Status Register 1 16 bit read 2 If the OVERRUN or OVERFLOW bits are set the data acquisition sequence has been halted because one of these error conditions has occurred...

Page 161: ...value Store a nonterminal count value Load Counter X Write 0xFFC0 2 ctr 1 to the Am9513A Command Register Write 0x0003 to the Am9513A Data Register Write 0xFF08 ctr to the Am9513A Command Register Poi...

Page 162: ...nce without reading the DAC FIFO flags after each subsequent transfer to keep from overfilling the FIFO This mode results in a significant performance increase in polled I O or interrupt servicing of...

Page 163: ...he update counter via RTSI programming Figure 5 7 Cyclic Waveform Programming Programmed Cycle Waveform Generation A superset of the waveform functionality exists if DAC data buffer is less than or eq...

Page 164: ...mming steps in Figure 5 8 The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter END START Clear the a...

Page 165: ...count buffer cycles in this mode If Counter 5 is being used for the update signal then only Counters 1 and 2 are available for cycle counting Once the cycle counter reaches the end of its count DAC up...

Page 166: ...the update interval counter Set the A4RCV bit in Command Register 2 Set the waveform generation mode Service update requests Clear the A4RCV bit in Command Register 2 Yes No Enable updating Program th...

Page 167: ...5 are available for updating To route these update signals the A side pin of the RTSI switch must be internally routed to the B side or trigger side Select a trigger line that is not being used The si...

Page 168: ...s programming sequence Counter n is configured to generate active low pulses as soon as the load arm counter command is written Programming the Waveform Cycle Counter Select the appropriate counter 1...

Page 169: ...m9513A Data Register to store the Counter 2 mode value Am9513A counter mode information can be found in Appendix E AMD Am9513A Data Sheet C225 Selects 5 MHz clock from SOURCE2 pin CB25 Selects 1 MHz c...

Page 170: ...s cleared by writing to the TMRREQ Clear Register or the DAC Clear Register Programming the Digital I O Circuitry The digital input circuitry is controlled and monitored using the Digital Input Regist...

Page 171: ...IO 64F 5 and specific programming requirements for the sample interval and sample counters are given earlier in this chapter For general programming details for Counters 1 2 and 5 and the programmable...

Page 172: ...ignals also appear at the AT MIO 64F 5 I O connector As shown in Table 5 2 two AT MIO 64F 5 signals are connected to pin A2 and two signals are connected to pin A4 The routing of these signals is furt...

Page 173: ...43 39 35 31 27 23 19 15 11 7 3 0 MSB LSB Figure 5 10 RTSI Switch Control Pattern In Figure 5 10 the fields labeled A6 through A0 and B6 through B0 are the 4 bit control fields for each RTSI switch pi...

Page 174: ...n a total of 56 times Only bit 0 of the word written to the RTSI Switch Shift Register is used The higher order bits are ignored Programming DMA Operations The AT MIO 64F 5 can be programmed so that t...

Page 175: ...to reinitialize mode DMA A and DMA B are continuously served in turn If dual channel DMA operation has been selected to service both analog outputs memory buffer A DMA channel A and memory buffer B DM...

Page 176: ...known value Because these values are lost when the board is powered down they are also stored in the onboard EEPROM for future referencing Figure 6 1 shows where information is stored in the EEPROM F...

Page 177: ...el 1 bipolar offset 112 Factory DAC Channel 0 bipolar gain 111 Factory DAC Channel 0 bipolar offset 110 Factory ADC gain 109 Factory ADC unipolar offset 108 Factory ADC postgain offset 107 Factory ADC...

Page 178: ...a known and calibrated state 0 1 2 7 3 4 5 6 Revision Subrevision MSB LSB 1111 15 1110 14 0010 2 0001 1 0000 0 1111 P 1110 O 0010 C 0001 B 0000 A Figure 6 2 Revision and Subrevision Field If the Revi...

Page 179: ...ly if the DAC FIFO is 2 048 values deep and a half full interrupt is generated then 1 024 values can be read This can have a significant performance impact on software speed 0 1 2 7 3 4 5 6 Reserved R...

Page 180: ...the AT MIO 64F 5 should be 10 times as accurate that is the equipment should have 0 001 10 ppm rated accuracy Practically speaking calibration equipment with four times the accuracy of the item under...

Page 181: ...The routine calibrates the circuitry to the external reference and then reads the internal reference This value is stored as a two s complement binary number in the onboard EEPROM for subsequent use b...

Page 182: ...nally CALDAC1 should be restored to its previous value If the three offset DACs are adjusted in this way there is no significant residual offset error and reading a grounded channel returns on average...

Page 183: ...ach analog output to 0 and measure the difference between each output and AOGND Finally it should measure the difference between AOGND and AIGND All these measurements need to be combined with the val...

Page 184: ...INL 1 LSB maximum over temperature 0 3 LSB typical Differential nonlinearity DNL 1 LSB maximum no missing codes over temperature 0 2 LSB typical Differential analog input ranges 5 V or 0 to 10 V soft...

Page 185: ...e ranges of error for which they must compensate If a calibration DAC is adjusted to center scale then the accuracy of the offset or gain that the DAC adjusts is the combined accuracy of the associate...

Page 186: ...y specification indicates the worst deviation from the ideal that the ADC permits A relative accuracy specification of 1 LSB is roughly equivalent to but not the same as a 1 2 LSB nonlinearity or inte...

Page 187: ...noise in the AT MIO 64F 5 is fairly Gaussian so the noise specifications given are the amounts of pure Gaussian noise required to produce our readings Overvoltage Protection The amount of input overvo...

Page 188: ...V step It may take as long as 100 sec for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Because of the problems with se...

Page 189: ...unt of possible deviation from ideal gain of the analog output circuitry expressed as a proportion of the gain The total linear error for a DAC at a given output voltage is the output voltage times th...

Page 190: ...Hz 1 kHz 100 Hz Base clock accuracy 0 01 Compatibility TTL compatible inputs and outputs Counter gate and source inputs are pulled up with 4 7 kW resistors onboard Counter input frequency 6 9 MHz maxi...

Page 191: ...National Instruments Corporation B 1 AT MIO 64F 5 User Manual Appendix B AT MIO 64F 5 I O Connector This appendix shows the pinout and signal names for the AT MIO 64F 5 100 pin I O connector...

Page 192: ...5 ACH22 ACH46 ACH23 ACH47 ACH24 ACH48 ACH25 ACH49 ACH26 ACH50 ACH27 ACH51 AISENSE AIGND ACH28 ACH52 ACH29 ACH53 ACH30 ACH54 ACH31 ACH55 ACH32 ACH56 ACH33 ACH57 ACH34 ACH58 ACH35 ACH59 ACH36 ACH60 ACH3...

Page 193: ...40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 FOUT GATE5 OUT2 EXTTMRTRIG GATE1 EXTCONV EXTTRIG SCANCLK 5 V BDIO3 BDIO2 BDIO1 BDIO0 DIG GN...

Page 194: ...ed this signal can be programmed to be driven by the board analog input ground in the DIFF and RSE analog input modes 20 DAC0 OUT AO GND Analog Channel 0 Output This pin supplies the voltage output of...

Page 195: ...conversions while the second high to low edge initiates the posttrigger sequence 39 EXTGATE DIG GND External Gate When EXTGATE is low A D conversions are inhibited When EXTGATE is high A D conversions...

Page 196: ...e Am9513A Counter 2 signal 46 OUT2 DIG GND OUTPUT2 This pin is from the Am9513A Counter 2 signal 47 SOURCE5 DIG GND SOURCE5 This pin is from the Am9513A Counter 5 signal 48 GATE5 DIG GND GATE5 This pi...

Page 197: ...SE 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ACH63 ACH62 ACH61 ACH60 ACH59 ACH58 ACH57 ACH56 ACH55 AC...

Page 198: ...ACH 16 27 as Channels 16 through 27 and ACH 40 51 as Channels 40 through 51 25 AI SENSE AI GND Analog Input Sense This pin serves as the reference mode when the board is in NRSE configuration If desir...

Page 199: ...he AMD Am9513A System Timing Controller integrated circuit Advanced Micro Devices Inc This controller is used on the AT MIO 64F 5 Copyright Advanced Micro Devices Inc 1989 Reprinted with permission of...

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Page 239: ...able Monday through Friday from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Techn...

Page 240: ...any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax P...

Page 241: ...FF RSE or NRSE ___________________________________________________ NI DAQ or LabWindows Version ___________________________________________________ Other Products Computer Make and Model _____________...

Page 242: ...Part Number 320487 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for yo...

Page 243: ...24 A D converter 3 6 ADC conversion timing 3 8 ADC Event Strobe Register Group 4 35 to 4 40 CONFIGMEMCLR Register 4 29 4 36 5 10 5 11 CONFIGMEMLD Register 4 29 4 37 5 10 5 11 DAQ Clear Register 4 38...

Page 244: ...4 to 5 15 update interval counter 5 23 to 5 24 waveform cycle counter 5 24 to 5 25 waveform cycle interval counter 5 25 register map 4 2 resetting after data acquisition operation 5 16 to 5 17 Am9513A...

Page 245: ...waveforms E 38 TC terminal count E 28 TEHWH TGVWH timing diagram E 40 timing I O circuitry 3 20 to 3 23 troubleshooting E 39 analog data acquisition rates multiple channel scanning rates A 5 single c...

Page 246: ...s 2 19 analog input specifications linear errors A 2 to A 3 equivalent gain and offset errors in 12 bit systems A 3 gain error A 2 to A 3 postgain offset error A 2 pregain offset error A 2 list of spe...

Page 247: ...ut 1 1 analog output 1 1 digital and timing I O 1 2 definition v illustration of 1 2 initializing 5 2 kit contents 1 3 optional equipment 1 4 to 1 5 optional software 1 3 parts locator diagram 2 2 reg...

Page 248: ...A4DRV 4 8 A4RCV 4 8 5 26 A6 through A0 5 29 ADC_BUSY 4 22 ADCDSP 4 11 ADCFIFOEF 4 20 5 5 5 16 5 30 5 31 ADCFIFOHF 4 19 5 16 5 30 5 31 ADCFIFOREQ 4 18 ADCREQ 4 13 ADIO 3 0 4 56 4 57 5 26 B6 through B0...

Page 249: ...2 0 4 9 DMATCA 4 20 5 23 5 31 DMATCB 4 20 5 23 5 31 DMATCINT 4 12 DRVAIS 4 14 EEPROMCD 4 21 EEPROMCS 4 5 EEPROMDATA 4 21 EISA_DMA 4 9 EXTREFDAC0 4 9 EXTREFDAC1 4 9 EXTTRIG_DIS 4 18 FIFO DAC 4 18 GATE...

Page 250: ...rea 1 1 6 3 equipment requirements 6 5 reference calibration 6 6 CFGMEMEF bit 4 21 CHAN_AIS bit 4 26 CHAN_BIP bit 4 27 CHAN_CAL bit 4 27 CHAN_DSP bit 4 29 CHAN_GHOST bit 4 29 CHAN_LAST bit 4 28 5 11 c...

Page 251: ...ister 3 4 11 to 4 15 Command Register 4 4 16 to 4 18 overview 4 4 register map 4 1 Status Register 1 4 19 to 4 21 Status Register 2 4 22 5 26 continuous channel scanning definition 5 7 programming 5 7...

Page 252: ...egister 4 33 DAC0DSP bit 4 17 DAC0REQ bit 4 14 DAC1 OUT signal 2 14 2 27 to 2 28 C 2 DAC1 Register 4 34 DAC1DSP bit 4 17 DAC1REQ bit 4 14 DACCMPLINT bit 4 12 DACCOMP bit 4 21 5 23 5 26 DACFIFOEF bit 4...

Page 253: ...scanned data acquisition 3 10 to 3 12 rates of data acquisition 3 8 single channel data acquisition 3 8 to 3 10 single read timing 3 8 theory of operation 3 8 to 3 10 data acquisition timing connecti...

Page 254: ...re 5 30 to 5 31 servicing update requests 5 26 single channel interleaved mode 5 31 DMA request generation bits for controlling 4 12 to 4 14 programming 5 30 to 5 31 DMACHA bit 4 12 DMACHAB 2 0 bit 4...

Page 255: ...18 D 2 External Strobe Register 4 49 EXTGATE signal data acquisition timing connections 2 32 definition 2 15 C 3 EXTREF signal analog output signal connections 2 27 to 2 28 definition 2 14 C 2 EXTREF...

Page 256: ...obe Register Group 4 45 to 4 50 Calibration DAC 0 Load Register 4 50 DMA Channel Clear Register 4 46 DMATCA Clear Register 4 47 5 23 5 30 5 31 DMATCB Clear Register 4 48 5 23 5 30 5 31 External Strobe...

Page 257: ...nge selection and gain 2 8 considerations for selecting ranges 2 8 installation See also configuration hardware installation 2 10 to 2 11 unpacking the AT MIO 64F 5 1 6 INTCHB 2 0 bit 4 15 integral no...

Page 258: ...er Manual Index 16 National Instruments Corporation L LabWindows software 1 3 linear errors equivalent gain and offset errors in 12 bit systems A 3 gain error A 2 to A 3 postgain offset error A 2 preg...

Page 259: ...l noise 2 37 to 2 38 system noise A 4 nonlinear errors differential nonlinearity A 4 integral nonlinearity A 3 relative accuracy A 3 nonreferenced single ended NRSE input configuration 2 7 definition...

Page 260: ...pplying a trigger 5 15 to 5 16 clearing analog input circuitry 5 10 cyclic waveform generation 5 18 to 5 19 multiple analog input channel configurations 5 11 programmed cycle waveform generation 5 19...

Page 261: ...ommand Register 4 53 Am9513A Data Register 4 52 Am9513A Status Register 4 54 programming 5 11 to 5 15 5 23 to 5 25 5 27 resetting after data acquisition operation 5 16 to 5 17 resource allocation prog...

Page 262: ...ced single ended RSE input RSI bit 4 59 RTSI bus interface circuitry 3 23 to 3 24 RTSI bus trigger line programming 5 27 to 5 28 RTSI clock configuration CLKMODEB 1 0 bit for selecting 4 16 timebase s...

Page 263: ...mmended configurations for ground referenced and floating signal sources 2 21 single ended connections floating signal RSE sources 2 25 general considerations 2 24 to 2 25 grounded signal NRSE sources...

Page 264: ...g output A 5 to A 6 digital I O A 7 operating environment A 7 physical characteristics A 7 power requirements A 7 storage environment A 7 timing I O A 7 square waves producing 2 33 SRC3SEL bit 4 18 SR...

Page 265: ...uisition timing connections 2 30 to 2 33 EXTCONV signal 2 31 EXTGATE signal 2 32 EXTSTROBE signal 2 30 to 2 31 EXTTMRTRIG signal 2 32 to 2 33 EXTTRIG signal 2 31 to 2 32 SCANCLK signal 2 30 general pu...

Page 266: ...earing analog output circuitry 5 23 cyclic waveform generation 5 18 to 5 19 programmed cycle waveform generation 5 19 to 5 21 pulsed cyclic waveform generation 5 21 to 5 23 selecting internal update c...

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