National Instruments AT-MIO-64F-5, User Manual

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Chapter 4 Register Map and Descriptions
© National Instruments Corporation 4-5 AT-MIO-64F-5 User Manual
Command Register 1
Command Register 1 contains 12 bits that control AT-MIO-64F-5 serial device access, and data
acquisition mode selection. The contents of this register are not defined upon power up and are
not cleared after a reset condition. This register should be initialized through software.
Address: Base a 00 (hex)
Type: Write-only
Word Size: 16-bit
Bit Map:
15 14 13 12 11 10 9 8
EEPROMCS SDATA SCLK SCANDIV DITHER INTGATE RETRIG_DIS DAQEN
MSB
7 6 5 4 3 2 1 0
SCANEN SCN2 CNT32/16* RTSITRIG 0 0 0 0
LSB
Bit Name Description
15 EEPROMCS EEPROM Chip Select Ð This bit controls the chip select of the
onboard EEPROM used to store calibration constants. When
EEPROMCS is set, the chip select signal to the EEPROM is
enabled. Before EEPROMCS is brought high, SCLK should first
be pulsed high to initialize the EEPROM circuitry.
14 SDATA Serial Data Ð This bit is used to transmit a single bit of data to the
EEPROM and both of the calibration DACs.
13 SCLK Serial Clock Ð A low-to-high transition of this bit clocks data from
SDATA into the EEPROM (when EEPROMCS is set) and the
calibration DAC. If EEPROMCS is cleared, toggling SCLK does
not affect the EEPROM. Serial data is always loaded into the
calibration DACs, but the information is not updated until after the
application of the appropriate load signal.
12 SCANDIV Scan Divide Ð This bit controls the configuration memory
sequencing during scanned data acquisition. If SCANDIV is set,
then sequencing is controlled by Counter 1 of the Am9513A
Counter/Timer. If SCANDIV is cleared, the configuration
memory is sequenced after each conversion during scanning.
11 DITHER Dither Ð When this bit is set, 0.5 LSBs of white Gaussian noise is
added to the selected analog input signal. By enabling DITHER
and using averaging, input resolution greater than 12 bits is
obtainable.