National Instruments AT-MIO-64F-5, User Manual

Page: 97 / 266

Chapter 4 Register Map and Descriptions
© National Instruments Corporation 4-13 AT-MIO-64F-5 User Manual
Bit Name Description (continued)
6 ADCREQ ADC Request Enable Ð This bit controls DMA requesting and
interrupt generation from an A/D conversion. If this bit is set, an
interrupt or DMA request is generated when an A/D conversion is
available in the FIFO. If this bit is cleared, no DMA request or
interrupt is generated following an A/D conversion. To select a
specific mode, refer to Table 4-3 for available modes and
associated bit patterns.
Table 4-3. DMA and Interrupt Modes
Interface Mode
IO_INT
DMACHA
DMACHB
ADCREQ
DAC1REQ DAC0REQ
Mode Description
0 1 0 0 0 1 Channel A to DAC0
0 1 0 0 1 0 Channel A to DAC1
0 1 0 0 1 1 Channel A to DAC0 and DAC1 (interleaved)
0 1 0 1 0 0 Channel A from ADC
0 0 1 0 0 1 Channel B to DAC0
0 0 1 0 1 0 Channel B to DAC1
0 0 1 0 1 1 Channel B to DAC0 and DAC1 (interleaved)
0 0 1 1 0 0 Channel B from ADC
0 1 1 0 0 0 Channel A and Channel B to DAC0 and DAC1 (double-buffered)
0 1 1 0 0 1 Channel A and Channel B to DAC0 (double-buffered)
0 1 1 0 1 0 Channel A and Channel B to DAC1 (double-buffered)
0 1 1 0 1 1 Channel A and Channel B to DAC0 and DAC1 (sync double-channel)
0 1 1 1 0 0 Channel A and Channel B from ADC (double-buffered)
0 1 1 1 0 1 Channel A from ADC, Channel B to DAC0
0 1 1 1 1 0 Channel A from ADC, Channel B to DAC1
0 1 1 1 1 1 Channel A from ADC, Channel B to DAC0 and DAC1 (interleaved)
1 0 0 0 0 1 Timer interrupt
1 0 0 0 1 0 Timer interrupt
1 0 0 0 1 1 Timer interrupt
1 0 0 1 0 0 ADC interrupt
1 0 0 1 0 1 ADC and timer interrupt
1 0 0 1 1 0 ADC and timer interrupt
1 0 0 1 1 1 ADC and timer interrupt
(continues)