National Instruments AT-MIO-64F-5, User Manual

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Register Map and Descriptions Chapter 4
AT-MIO-64F-5 User Manual 4-18 © National Instruments Corporation
Bit Name Description (continued)
6 DB_DIS Double Buffering Disable Ð This bit controls the updating of the
DACs. If DB_DIS is set, writes to the DACs in immediate and
delayed update mode are neither double-buffered nor deglitched.
If DB_DIS is cleared, the DACs are double-buffered and
deglitched.
5 CYCLICSTOP Cyclic Stop Enable Ð This bit controls when a DAC sequence
terminates. If this bit is set when operating the DACs through the
FIFO in a cyclic mode, the DAC circuitry will halt when the next
end of buffer is encountered. If this bit is clear when the DACs are
in a cyclic mode, the DAC circuitry will restart transmission of the
buffer after reaching the final point in the buffer. This bit is
functional only when the DAC circuitry is in cyclic mode and data
is stored exclusively in the DAC FIFO.
4 ADCFIFOREQ ADC FIFO Request Ð This bit controls the ADC FIFO Interrupt
and DMA Request mode. When ADCFIFOREQ is set, ADC
interrupt/DMA requests are generated when the ADC FIFO is half-
full. In this case, the request is removed only when the ADC FIFO
has been emptied of all its data. When ADCFIFOREQ is cleared,
ADC interrupt/DMA requests are generated when a single
conversion is available in the FIFO. In this case, the request is
removed when the ADC FIFO is empty.
3 SRC3SEL Source 3 Select Ð This bit is used to configure the signal connected
to Source 3 of the Am9513 Counter/Timer. If SRC3SEL is set,
Source 3 is connected to the DAC FIFO retransmit signal. In the
FIFO programmed cycle waveform modes, this bit should be set so
the counter can access to the DAC FIFO retransmit signal. If
SRC3SEL is cleared, Source 3 is connected to the SCANCLK
signal.
2 GATE2SEL Gate 2 Select Ð This bit is used to configure the signal connected to
Gate 2 of the Am9513 Counter/Timer. If GATE2SEL is set, Gate
2 is connected to Out 1 of the Am9513. This bit should be set
when using the FIFO pulsed waveform generation mode. If
GATE2SEL is cleared, Gate 2 is connected to the internal Gate 2
circuitry on the AT-MIO-64F-5.
1 FIFO/DAC FIFO or DAC Write Select Ð This bit controls the destination of
writes to the analog output DACs. DMA transfers to the DACs are
always buffered by the DAC FIFO. Programmed I/O writes are
routed either to the DACs or through the DAC FIFO by using the
FIFO/DAC bit. If FIFO/DAC is set, programmed I/O writes to the
DACs are buffered by the DAC FIFO. If FIFO/DAC is cleared,
programmed I/O writes to the DACs bypass the DAC FIFO and
are transmitted directly to the DACs.
0 EXTTRIG_DIS External Trigger Disable Ð This bit gates the EXTTRIG* signal
from the I/O connector. If EXTTRIG_DIS is set, triggers from
EXTTRIG* are ignored by the AT-MIO-64F-5 circuitry. If this bit
is cleared, triggers from the EXTTRIG* signal are able to initiate
data acquisition sequences.