National Instruments AT-MIO-64F-5, User Manual

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Register Map and Descriptions Chapter 4
AT-MIO-64F-5 User Manual 4-12 © National Instruments Corporation
Bit Name Description (continued)
12 DMATCINT DMA Terminal Count Interrupt Enable Ð This bit controls the
generation of an interrupt when a DMA terminal count pulse is
received from the DMA controller in the PC AT. If DMATCINT
is set, an interrupt request is generated when the DMA controller
transfers the final value on the primary DMA channel, channel A,
or the secondary DMA channel, channel B. The interrupt request
is serviced by strobing the appropriate DMATC Clear Register.
When DMATCINT is cleared, no DMA terminal count interrupts
are generated.
11 DACCMPLINT DAC Complete Interrupt Enable Ð This bit controls the generation
of an interrupt when a DAC sequence completes. If
DACCMPLINT is set, an interrupt request is generated when the
sequence completes. The interrupt request is serviced by strobing
the TMRREQ Clear or DAC Clear Register. When
DACCMPLINT is cleared, completion of a sequence does not
generate an interrupt. A DAC sequence ends by running its course
or when an error condition occurs such as UNDERFLOW.
10 DAQCMPLINT DAQ Complete Interrupt Enable Ð This bit controls the generation
of an interrupt when a data acquisition sequence completes. If
DAQCMPLINT is set, an interrupt request is generated when the
data acquisition operation completes. The interrupt request is
serviced by strobing the DAQ Clear Register. When
DAQCMPLINT is cleared, completion of a data acquisition
sequence does not generate an interrupt. A data acquisition
sequence ends by running its course or when an error condition
occurs such as OVERRUN or OVERFLOW.
9 I/O_INT Input/Output Interrupt Enable Ð This bit, along with the
appropriate mode bits, enables and disables I/O interrupts
generated from the AT-MIO-64F-5. To select a specific mode,
refer to Table 4-3 for available modes and associated bit patterns.
8 DMACHA DMA Channel A Enable Ð This bit controls the generation of
DMA requests on DMA channel A as selected in Command
Register 2. DMA requests are generated from A/D conversions as
well as from timer updates. If DMACHA is set, then requesting is
enabled for DMA channel A. If DMACHA is cleared, no DMA
requests are generated on DMA channel A. To select a specific
mode, refer to Table 4-3 for available modes and associated bit
patterns.
7 DMACHB DMA Channel B Enable Ð This bit controls the generation of
DMA requests on DMA channel B as selected in Command
Register 2. DMA requests are generated from A/D conversions as
well as from timer updates. If DMACHB is set, requesting is
enabled for DMA channel B. If DMACHB is cleared, no DMA
requests are generated on DMA channel B. To select a specific
mode, refer to Table 4-3 for available modes and associated bit
patterns.