Keysight Technologies 16860 Series, Service Manual

Page: 92 / 138

5 Troubleshooting
92 Keysight 16860 Series Portable Logic Analyzers Service Guide
Comparator Programming Test
The purpose of this test is to verify the programming path to each of the comparators.
Comparator/DAC Test
This test is executed only if all probes are detached.
This test uses the pod, bonus, and calibration DACs, the calibration oscillator (implemented in the
interface FPGA), the comparators, the connections between the comparators and the Analysis chip,
and the activity indicators in the Analysis chip. We verify that we can use the DACs to control the
data input to the comparators. We verify that each comparator data channel produces output. We
verify that each comparator output is connected to each ASIC data input.
Comparator Delay Test
The comparator delay test verifies the integrity of all the delay line elements for each delay line in the
comparators. Each delay line consists of 11 delay elements. When set for maximum delay, all 11
elements are connected in series. If any element is faulty, then data will not propagate through the
comparator. If this is the only test failing, then it is almost certainly a bad comparator.
Comparator Zero-Hold Cal Test
Tests the delay elements for each delay line in the comparators. It tests that each delay line can
increase its delay in a linear way through a range of delay values.
Comparator Calibrations Test
The purpose of this test is to verify that each of the comparator one-time calibrations can
successfully be performed. This verifies that all of the calibration circuitry and components are within
the tolerance limits required for proper calibration. This test is executed only if all probes are
detached.
Acquisition Memory Write/Read Test
This test checks that each acquisition chip can write data to DDR acquisition memory and read the
same data back.
Acquisition Memory Cell Test
Tests every bit of the DDR acquisition memory. The test verifies that every bit can be written to 0 and
written to 1 and read back accurately.
ATB (AXIe Trigger Bus) Test
This test verifies the ATB signal connections between the acquisition chips, the interface FPGA and
the two 8-bit transceiver chips.
To exit the test system
1 Close the self-test dialog. No additional actions are required.