REL1.3
Page 52 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
64
HSCIF1_HRX1(GP7_14)
IRQ4/
AC29
I, 3.3V CMOS
High Speed Serial Communication
Interface (HSCIF1) Serial Data
Receiver.
65
MSIOF1_RXD/HRTS1#(GP7
_18)
IRQ8/
AB27
I, 3.3V CMOS
SPI receive data input (or) High
Speed
Serial
Communication
Interface (HSCIF1) ready to receive
handshake signal.
66
GND
NA
Power
Ground.
67
MSIOF1_SS2/HSCK1(GP7_
16)
IRQ6 /
AC27
O, 3.3V CMOS
SPI frame synchronization signal 2.
68
PRESETOUT#
PRESETOUT#/
U5
O, 3.3V CMOS
Reset output.
Note: MLBP_SIG_P is optionally
connected to this pin through
resistor and default not populated.
69
MSIOF1_SCK(GP2_29)
AUDIO_CLKB/
AC30
IO, 3.3V CMOS
SPI serial clock.
70
NMI
NMI/
AL16
I, 3.3V CMOS/
10K PU
External Non maskable Interrupt.
Note: MLBP_SIG_N is optionally
connected to this pin through
resistor and default not populated.
71
AUDIO_CLKOUT(GP2_31/
MD5)
1
AUDIO_CLKOUT/M
D5/
AE31
O, 3.3V CMOS/
100K PU
Audio clock out.
72
NC
NA
-
Default NC.
Note: MLBP_CLK_P is optionally
connected to this pin through
resistor and default not populated.
73
AUDIO_CLKA(GP2_28)
AUDIO_CLKA/
AD31
I, 3.3V CMOS
Audio Clock A.
74
NC
NA
-
Default NC.
Note: MLBP_CLK_N is optionally
connected to this pin through
resistor and default not populated
.
75
GND
NA
Power
Ground.
76
GND
NA
Power
Ground.
77
SCIF1_TX1(GP2_24)
SSI_SDATA8/
AA25
O, 3.3V CMOS
Serial Communication Interface
(SCIF1) Serial Data Transmitter.
78
DU0_DOTCLKIN(GP6_31)
DU0_DOTCLKIN /
AG17
I, 3.3V CMOS
DU0 dot clock input.
Note: MLBP_DAT_P is optionally
connected to this pin through
resistor and default not populated.