REL1.3
Page 39 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.7.1
Parallel Camera Interface
The RZ/G1M/G1N Qseven SOM supports three parallel camera interfaces on Expansion connector1. RZ/G1M/G1N
CPU’s VIN0, VIN1 & VNI2 channels are used for parallel camera interfaces.
RZ/G1M/G1N
CPU’s VIN0 is supported with
8bit/16bit/24bit camera interfaces, VIN1 is supported with 8bit/16bit camera interface and VIN2 is supported with
8bit camera interface on Expansion connector1.
The RZ/G1M/G1N
CPU’s
Video Input Module (VIN) is a video capture module that supports YCbCr-422 data through
the ITU-R BT.601, ITU-R BT.656 or ITU-R BT.709 interface and RGB data through the ITUR BT.601 or ITU-R BT.709
interface. The VIN supports Vertical and Horizontal Scaling where the image can be scaled up and down up to three
times in the vertical and two times in the horizontal directions. Also it has two clipping circuits, which independently
handle images with up to 2048 × 2048 pixels. The VIN provides a colour space conversion function from YCbCr-422 to
RGB, a format conversion function from RGB to ARGB.
For more details, refer Expansion connector1 pins on
Table 5: Parallel Camera Interface Pin Assignment on Expansion connector1
RZ/G1M/G1N
VIN Channel
VIN Channel
Data Width
Parallel Camera Interface Pins on RZ/G1M/G1N Qseven SOM
Expansion Connector1
VIN0
8bit
7,9,11,13,15,17,19,21,61,65,69
16bit
7,9,11,13,15,17,19,21,25,27,29,31,33,35,37,39,61,65,69
24bit
7,9,11,13,15,17,19,21,25,27,29,31,33,35,37,39,43,45,47,49,51,53,55,57,61,65,69
VIN1
8bit (GroupC)
4,6,8,10,12,14,16,18,20,22,24,63,67
16bit (GroupB)
1,3,18,20,22,24,34,36,38,40,42,50,52,54,56,58,63,64,66,67
VIN2
8bit
25,27,29,31,33,35,45,47,49,51,53,55,57
Note: In RZ/G1M/G1N CPU, DU1 & VIN1 (some pins) are multiplexed in same pins and so DU1 cannot be supported
when VIN1 is supported in 16bit mode. If VIN1 is supported in 8bit mode, then DU1 also can be supported.
Note: In RZ/G1M/G1N CPU, VIN0 & VIN2 are multiplexed in same pins and so VIN2 cannot be supported when VIN0 is
supported in 16bit/24bit mode. If VIN0 is supported in 8bit mode, then VIN2 also can be supported in 8bit mode.
Note:
In RZ/G1M/G1N CPU, SCIF4 & VIN1 (some pins) are multiplexed in same pins and so SCIF4 cannot be supported
when VI1 is supported in 16bit mode. If VIN1 is supported in 8bit mode, then SCIF4 also can be supported.
