REL1.3
Page 13 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Expansion Connector1 Interfaces
•
Parallel Camera x 3 Ports
(VIN0
–
8bit/16bit/24bit, VIN1
–
8bit/16bit, VIN2
–
8bit)
4,5
•
Parallel LCD (24bpp RGB) x 1 Port
4
•
Data UART x 1 Port
6
Expansion Connector2 Interfaces
•
SSI/I2S x 1 Port
•
CAN x 1 Port
•
SPI x 1 Port
7
•
Data UART x 2 Ports
7
•
PWM x 1 Port
•
Memory Bus (16bit Sync/Async)
General Specification
•
Power Supply
:
5V,1.2A
•
Power IN connector for Standalone usage (Optional)
•
Form Factor
:
70mm x 70mm (Qseven® Specification Version 2.0)
1
In RZ/G1M CPU, USB3.0 and SATA0 are multiplexed in same pins and so either one interface only can be used at a
time. By default, USB3.0 is supported.
2
In RZ/G1M CPU, PCIe and SATA1 are multiplexed in same pins and so either one interface only can be used at a time.
By default, PCIe is supported.
3
In RZ/G1N CPU, USB3.0, PCIe & SATA are multiplexed in same pins and so either one interface only can be used at a
time. By default USB3.0 is supported.
4
In RZ/G1M/G1N CPU, DU1 & VIN1 (some pins) are multiplexed in same pins and so DU1 cannot be supported when
VIN1 is supported in 16bit mode. If VIN1 is supported in 8bit mode, then DU1 also can be supported.
5
In RZ/G1M/G1N CPU, VIN0 & VIN2 are multiplexed in same pins and so VIN2 cannot be supported when VIN0 is
supported in 16bit/24bit mode. If VIN0 is supported in 8bit mode, then VIN2 also can be supported in 8bit mode.
6
In RZ/G1M/G1N CPU, SCIF4 & VIN1 (some pins) are multiplexed in same pins and so SCIF4 cannot be supported when
VI1 is supported in 16bit mode. If VIN1 is supported in 8bit mode, then SCIF4 also can be supported.
7
In RZ/G1M/G1N CPU, MSIOF1 and HSCIF1 are multiplexed in same pins and so MSIOF1 cannot be supported when
HSCIF1is supported with Hardware flow control signals. If HSCIF1is supported without Hardware flow control signals,
then MSIOF1 also can be supported.
